Merge #511
511: Fix wrong pin configuration in STM32's SPI v3. r=matoushybl a=matoushybl Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
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commit
2d620df9d6
@ -1,9 +1,8 @@
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#![macro_use]
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#![macro_use]
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use crate::dma::NoDma;
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use crate::dma::NoDma;
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use crate::gpio::{AnyPin, Pin};
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use crate::gpio::sealed::Pin;
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use crate::pac::gpio::vals::{Afr, Moder};
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use crate::gpio::AnyPin;
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use crate::pac::gpio::Gpio;
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use crate::pac::spi;
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use crate::pac::spi;
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use crate::spi::{
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use crate::spi::{
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ByteOrder, Config, Error, Instance, MisoPin, MosiPin, RxDmaChannel, SckPin, TxDmaChannel,
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ByteOrder, Config, Error, Instance, MisoPin, MosiPin, RxDmaChannel, SckPin, TxDmaChannel,
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@ -68,12 +67,18 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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let miso = miso.degrade_optional();
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let miso = miso.degrade_optional();
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unsafe {
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unsafe {
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sck.as_ref()
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sck.as_ref().map(|x| {
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.map(|x| Self::configure_pin(x.block(), x.pin() as _, sck_af));
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x.set_as_af(sck_af, crate::gpio::sealed::AFType::OutputPushPull);
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mosi.as_ref()
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x.set_speed(crate::gpio::Speed::VeryHigh);
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.map(|x| Self::configure_pin(x.block(), x.pin() as _, mosi_af));
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});
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miso.as_ref()
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mosi.as_ref().map(|x| {
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.map(|x| Self::configure_pin(x.block(), x.pin() as _, miso_af));
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x.set_as_af(mosi_af, crate::gpio::sealed::AFType::OutputPushPull);
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x.set_speed(crate::gpio::Speed::VeryHigh);
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});
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miso.as_ref().map(|x| {
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x.set_as_af(miso_af, crate::gpio::sealed::AFType::Input);
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x.set_speed(crate::gpio::Speed::VeryHigh);
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});
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}
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}
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let pclk = T::frequency();
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let pclk = T::frequency();
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@ -122,16 +127,6 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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}
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}
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}
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}
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unsafe fn configure_pin(block: Gpio, pin: usize, af_num: u8) {
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let (afr, n_af) = if pin < 8 { (0, pin) } else { (1, pin - 8) };
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block.moder().modify(|w| w.set_moder(pin, Moder::ALTERNATE));
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block.afr(afr).modify(|w| w.set_afr(n_af, Afr(af_num)));
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}
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unsafe fn unconfigure_pin(block: Gpio, pin: usize) {
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block.moder().modify(|w| w.set_moder(pin, Moder::ANALOG));
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}
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fn compute_baud_rate(clocks: Hertz, freq: Hertz) -> u8 {
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fn compute_baud_rate(clocks: Hertz, freq: Hertz) -> u8 {
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match clocks.0 / freq.0 {
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match clocks.0 / freq.0 {
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0 => unreachable!(),
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0 => unreachable!(),
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@ -322,15 +317,9 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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impl<'d, T: Instance, Tx, Rx> Drop for Spi<'d, T, Tx, Rx> {
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impl<'d, T: Instance, Tx, Rx> Drop for Spi<'d, T, Tx, Rx> {
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fn drop(&mut self) {
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fn drop(&mut self) {
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unsafe {
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unsafe {
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self.sck
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self.sck.as_ref().map(|x| x.set_as_analog());
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.as_ref()
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self.mosi.as_ref().map(|x| x.set_as_analog());
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.map(|x| Self::unconfigure_pin(x.block(), x.pin() as _));
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self.miso.as_ref().map(|x| x.set_as_analog());
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self.mosi
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.as_ref()
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.map(|x| Self::unconfigure_pin(x.block(), x.pin() as _));
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self.miso
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.as_ref()
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.map(|x| Self::unconfigure_pin(x.block(), x.pin() as _));
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}
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}
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}
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}
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}
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}
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@ -1,9 +1,8 @@
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#![macro_use]
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#![macro_use]
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use crate::dma::NoDma;
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use crate::dma::NoDma;
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use crate::gpio::{AnyPin, Pin};
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use crate::gpio::sealed::Pin;
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use crate::pac::gpio::vals::{Afr, Moder};
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use crate::gpio::AnyPin;
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use crate::pac::gpio::Gpio;
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use crate::pac::spi;
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use crate::pac::spi;
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use crate::spi::{
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use crate::spi::{
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ByteOrder, Config, Error, Instance, MisoPin, MosiPin, RxDmaChannel, SckPin, TxDmaChannel,
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ByteOrder, Config, Error, Instance, MisoPin, MosiPin, RxDmaChannel, SckPin, TxDmaChannel,
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@ -70,14 +69,18 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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let miso = miso.degrade_optional();
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let miso = miso.degrade_optional();
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unsafe {
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unsafe {
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sck.as_ref()
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sck.as_ref().map(|x| {
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.map(|x| Self::configure_pin(x.block(), x.pin() as _, sck_af));
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x.set_as_af(sck_af, crate::gpio::sealed::AFType::OutputPushPull);
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//sck.block().otyper().modify(|w| w.set_ot(Pin::pin(sck) as _, crate::pac::gpio::vals::Ot::PUSHPULL));
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x.set_speed(crate::gpio::Speed::VeryHigh);
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sck.as_ref()
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});
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.map(|x| Self::configure_pin(x.block(), x.pin() as _, mosi_af));
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mosi.as_ref().map(|x| {
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//mosi.block().otyper().modify(|w| w.set_ot(Pin::pin(mosi) as _, crate::pac::gpio::vals::Ot::PUSHPULL));
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x.set_as_af(mosi_af, crate::gpio::sealed::AFType::OutputPushPull);
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sck.as_ref()
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x.set_speed(crate::gpio::Speed::VeryHigh);
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.map(|x| Self::configure_pin(x.block(), x.pin() as _, miso_af));
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});
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miso.as_ref().map(|x| {
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x.set_as_af(miso_af, crate::gpio::sealed::AFType::Input);
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x.set_speed(crate::gpio::Speed::VeryHigh);
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});
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}
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}
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let pclk = T::frequency();
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let pclk = T::frequency();
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@ -137,19 +140,6 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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}
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}
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}
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}
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unsafe fn configure_pin(block: Gpio, pin: usize, af_num: u8) {
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let (afr, n_af) = if pin < 8 { (0, pin) } else { (1, pin - 8) };
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block.moder().modify(|w| w.set_moder(pin, Moder::ALTERNATE));
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block.afr(afr).modify(|w| w.set_afr(n_af, Afr(af_num)));
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block
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.ospeedr()
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.modify(|w| w.set_ospeedr(pin, crate::pac::gpio::vals::Ospeedr::VERYHIGHSPEED));
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}
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unsafe fn unconfigure_pin(block: Gpio, pin: usize) {
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block.moder().modify(|w| w.set_moder(pin, Moder::ANALOG));
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}
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fn compute_baud_rate(clocks: Hertz, freq: Hertz) -> u8 {
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fn compute_baud_rate(clocks: Hertz, freq: Hertz) -> u8 {
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match clocks.0 / freq.0 {
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match clocks.0 / freq.0 {
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0 => unreachable!(),
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0 => unreachable!(),
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@ -346,15 +336,9 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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impl<'d, T: Instance, Tx, Rx> Drop for Spi<'d, T, Tx, Rx> {
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impl<'d, T: Instance, Tx, Rx> Drop for Spi<'d, T, Tx, Rx> {
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fn drop(&mut self) {
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fn drop(&mut self) {
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unsafe {
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unsafe {
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self.sck
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self.sck.as_ref().map(|x| x.set_as_analog());
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.as_ref()
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self.mosi.as_ref().map(|x| x.set_as_analog());
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.map(|x| Self::unconfigure_pin(x.block(), x.pin() as _));
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self.miso.as_ref().map(|x| x.set_as_analog());
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self.mosi
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.as_ref()
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.map(|x| Self::unconfigure_pin(x.block(), x.pin() as _));
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self.miso
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.as_ref()
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.map(|x| Self::unconfigure_pin(x.block(), x.pin() as _));
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}
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}
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}
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}
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}
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}
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