518: Incrementally merge STM32 SPI versions, Part 1 r=Dirbaio a=GrantM11235



Co-authored-by: Grant Miller <GrantM11235@gmail.com>
This commit is contained in:
bors[bot] 2021-12-07 04:45:14 +00:00 committed by GitHub
commit 2e6c3b22b8
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
4 changed files with 398 additions and 555 deletions

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@ -1,15 +1,23 @@
#![macro_use]
use crate::dma;
use crate::gpio::sealed::{AFType, Pin};
use crate::gpio::{AnyPin, NoPin, OptionalPin};
use crate::pac::spi::vals;
use crate::peripherals;
use crate::rcc::RccPeripheral;
use crate::time::Hertz;
use core::marker::PhantomData;
use embassy::util::Unborrow;
use embassy_hal_common::unborrow;
#[cfg_attr(spi_v1, path = "v1.rs")]
#[cfg_attr(spi_f1, path = "v1.rs")]
#[cfg_attr(spi_v2, path = "v2.rs")]
#[cfg_attr(spi_v3, path = "v3.rs")]
mod _version;
use crate::{dma, peripherals, rcc::RccPeripheral};
pub use _version::*;
use crate::gpio::OptionalPin;
#[derive(Debug)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Error {
@ -31,6 +39,48 @@ enum WordSize {
SixteenBit,
}
impl WordSize {
#[cfg(any(spi_v1, spi_f1))]
fn dff(&self) -> vals::Dff {
match self {
WordSize::EightBit => vals::Dff::EIGHTBIT,
WordSize::SixteenBit => vals::Dff::SIXTEENBIT,
}
}
#[cfg(spi_v2)]
fn ds(&self) -> vals::Ds {
match self {
WordSize::EightBit => vals::Ds::EIGHTBIT,
WordSize::SixteenBit => vals::Ds::SIXTEENBIT,
}
}
#[cfg(spi_v2)]
fn frxth(&self) -> vals::Frxth {
match self {
WordSize::EightBit => vals::Frxth::QUARTER,
WordSize::SixteenBit => vals::Frxth::HALF,
}
}
#[cfg(spi_v3)]
fn dsize(&self) -> u8 {
match self {
WordSize::EightBit => 0b0111,
WordSize::SixteenBit => 0b1111,
}
}
#[cfg(spi_v3)]
fn _frxth(&self) -> vals::Fthlv {
match self {
WordSize::EightBit => vals::Fthlv::ONEFRAME,
WordSize::SixteenBit => vals::Fthlv::ONEFRAME,
}
}
}
#[non_exhaustive]
pub struct Config {
pub mode: Mode,
@ -46,6 +96,284 @@ impl Default for Config {
}
}
pub struct Spi<'d, T: Instance, Tx, Rx> {
sck: Option<AnyPin>,
mosi: Option<AnyPin>,
miso: Option<AnyPin>,
txdma: Tx,
rxdma: Rx,
current_word_size: WordSize,
phantom: PhantomData<&'d mut T>,
}
impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
pub fn new<F>(
_peri: impl Unborrow<Target = T> + 'd,
sck: impl Unborrow<Target = impl SckPin<T>>,
mosi: impl Unborrow<Target = impl MosiPin<T>>,
miso: impl Unborrow<Target = impl MisoPin<T>>,
txdma: impl Unborrow<Target = Tx>,
rxdma: impl Unborrow<Target = Rx>,
freq: F,
config: Config,
) -> Self
where
F: Into<Hertz>,
{
unborrow!(sck, mosi, miso, txdma, rxdma);
let sck_af = sck.af_num();
let mosi_af = mosi.af_num();
let miso_af = miso.af_num();
let sck = sck.degrade_optional();
let mosi = mosi.degrade_optional();
let miso = miso.degrade_optional();
unsafe {
sck.as_ref().map(|x| {
x.set_as_af(sck_af, AFType::OutputPushPull);
#[cfg(any(spi_v2, spi_v3))]
x.set_speed(crate::gpio::Speed::VeryHigh);
});
mosi.as_ref().map(|x| {
x.set_as_af(mosi_af, AFType::OutputPushPull);
#[cfg(any(spi_v2, spi_v3))]
x.set_speed(crate::gpio::Speed::VeryHigh);
});
miso.as_ref().map(|x| {
x.set_as_af(miso_af, AFType::Input);
#[cfg(any(spi_v2, spi_v3))]
x.set_speed(crate::gpio::Speed::VeryHigh);
});
}
let pclk = T::frequency();
let br = Self::compute_baud_rate(pclk, freq.into());
#[cfg(any(spi_v1, spi_f1))]
unsafe {
T::enable();
T::reset();
T::regs().cr2().modify(|w| {
w.set_ssoe(false);
});
T::regs().cr1().modify(|w| {
w.set_cpha(
match config.mode.phase == Phase::CaptureOnSecondTransition {
true => vals::Cpha::SECONDEDGE,
false => vals::Cpha::FIRSTEDGE,
},
);
w.set_cpol(match config.mode.polarity == Polarity::IdleHigh {
true => vals::Cpol::IDLEHIGH,
false => vals::Cpol::IDLELOW,
});
w.set_mstr(vals::Mstr::MASTER);
w.set_br(vals::Br(br));
w.set_spe(true);
w.set_lsbfirst(match config.byte_order {
ByteOrder::LsbFirst => vals::Lsbfirst::LSBFIRST,
ByteOrder::MsbFirst => vals::Lsbfirst::MSBFIRST,
});
w.set_ssi(true);
w.set_ssm(true);
w.set_crcen(false);
w.set_bidimode(vals::Bidimode::UNIDIRECTIONAL);
if mosi.is_none() {
w.set_rxonly(vals::Rxonly::OUTPUTDISABLED);
}
w.set_dff(WordSize::EightBit.dff())
});
}
#[cfg(spi_v2)]
unsafe {
T::enable();
T::reset();
T::regs().cr2().modify(|w| {
w.set_frxth(WordSize::EightBit.frxth());
w.set_ds(WordSize::EightBit.ds());
w.set_ssoe(false);
});
T::regs().cr1().modify(|w| {
w.set_cpha(
match config.mode.phase == Phase::CaptureOnSecondTransition {
true => vals::Cpha::SECONDEDGE,
false => vals::Cpha::FIRSTEDGE,
},
);
w.set_cpol(match config.mode.polarity == Polarity::IdleHigh {
true => vals::Cpol::IDLEHIGH,
false => vals::Cpol::IDLELOW,
});
w.set_mstr(vals::Mstr::MASTER);
w.set_br(vals::Br(br));
w.set_lsbfirst(match config.byte_order {
ByteOrder::LsbFirst => vals::Lsbfirst::LSBFIRST,
ByteOrder::MsbFirst => vals::Lsbfirst::MSBFIRST,
});
w.set_ssi(true);
w.set_ssm(true);
w.set_crcen(false);
w.set_bidimode(vals::Bidimode::UNIDIRECTIONAL);
w.set_spe(true);
});
}
#[cfg(spi_v3)]
unsafe {
T::enable();
T::reset();
T::regs().ifcr().write(|w| w.0 = 0xffff_ffff);
T::regs().cfg2().modify(|w| {
//w.set_ssoe(true);
w.set_ssoe(false);
w.set_cpha(
match config.mode.phase == Phase::CaptureOnSecondTransition {
true => vals::Cpha::SECONDEDGE,
false => vals::Cpha::FIRSTEDGE,
},
);
w.set_cpol(match config.mode.polarity == Polarity::IdleHigh {
true => vals::Cpol::IDLEHIGH,
false => vals::Cpol::IDLELOW,
});
w.set_lsbfrst(match config.byte_order {
ByteOrder::LsbFirst => vals::Lsbfrst::LSBFIRST,
ByteOrder::MsbFirst => vals::Lsbfrst::MSBFIRST,
});
w.set_ssm(true);
w.set_master(vals::Master::MASTER);
w.set_comm(vals::Comm::FULLDUPLEX);
w.set_ssom(vals::Ssom::ASSERTED);
w.set_midi(0);
w.set_mssi(0);
w.set_afcntr(vals::Afcntr::CONTROLLED);
w.set_ssiop(vals::Ssiop::ACTIVEHIGH);
});
T::regs().cfg1().modify(|w| {
w.set_crcen(false);
w.set_mbr(vals::Mbr(br));
w.set_dsize(WordSize::EightBit.dsize());
});
T::regs().cr2().modify(|w| {
w.set_tsize(0);
w.set_tser(0);
});
T::regs().cr1().modify(|w| {
w.set_ssi(false);
w.set_spe(true);
});
}
Self {
sck,
mosi,
miso,
txdma,
rxdma,
current_word_size: WordSize::EightBit,
phantom: PhantomData,
}
}
fn compute_baud_rate(clocks: Hertz, freq: Hertz) -> u8 {
match clocks.0 / freq.0 {
0 => unreachable!(),
1..=2 => 0b000,
3..=5 => 0b001,
6..=11 => 0b010,
12..=23 => 0b011,
24..=39 => 0b100,
40..=95 => 0b101,
96..=191 => 0b110,
_ => 0b111,
}
}
fn set_word_size(&mut self, word_size: WordSize) {
if self.current_word_size == word_size {
return;
}
#[cfg(any(spi_v1, spi_f1))]
unsafe {
T::regs().cr1().modify(|reg| {
reg.set_spe(false);
reg.set_dff(word_size.dff())
});
T::regs().cr1().modify(|reg| {
reg.set_spe(true);
});
}
#[cfg(spi_v2)]
unsafe {
T::regs().cr1().modify(|w| {
w.set_spe(false);
});
T::regs().cr2().modify(|w| {
w.set_frxth(word_size.frxth());
w.set_ds(word_size.ds());
});
T::regs().cr1().modify(|w| {
w.set_spe(true);
});
}
#[cfg(spi_v3)]
unsafe {
T::regs().cr1().modify(|w| {
w.set_csusp(true);
});
while T::regs().sr().read().eot() {}
T::regs().cr1().modify(|w| {
w.set_spe(false);
});
T::regs().cfg1().modify(|w| {
w.set_dsize(word_size.dsize());
});
T::regs().cr1().modify(|w| {
w.set_csusp(false);
w.set_spe(true);
});
}
self.current_word_size = word_size;
}
}
impl<'d, T: Instance, Tx, Rx> Drop for Spi<'d, T, Tx, Rx> {
fn drop(&mut self) {
unsafe {
self.sck.as_ref().map(|x| x.set_as_analog());
self.mosi.as_ref().map(|x| x.set_as_analog());
self.miso.as_ref().map(|x| x.set_as_analog());
}
}
}
trait RegsExt {
fn tx_ptr<W>(&self) -> *mut W;
fn rx_ptr<W>(&self) -> *mut W;
}
impl RegsExt for crate::pac::spi::Spi {
fn tx_ptr<W>(&self) -> *mut W {
#[cfg(not(spi_v3))]
let dr = self.dr();
#[cfg(spi_v3)]
let dr = self.txdr();
dr.ptr() as *mut W
}
fn rx_ptr<W>(&self) -> *mut W {
#[cfg(not(spi_v3))]
let dr = self.dr();
#[cfg(spi_v3)]
let dr = self.rxdr();
dr.ptr() as *mut W
}
}
pub(crate) mod sealed {
use super::*;
@ -135,6 +463,26 @@ crate::pac::peripheral_pins!(
};
);
macro_rules! impl_nopin {
($inst:ident, $signal:ident) => {
impl $signal<peripherals::$inst> for NoPin {}
impl sealed::$signal<peripherals::$inst> for NoPin {
fn af_num(&self) -> u8 {
0
}
}
};
}
crate::pac::peripherals!(
(spi, $inst:ident) => {
impl_nopin!($inst, SckPin);
impl_nopin!($inst, MosiPin);
impl_nopin!($inst, MisoPin);
};
);
macro_rules! impl_dma {
($inst:ident, {dmamux: $dmamux:ident}, $signal:ident, $request:expr) => {
impl<T> sealed::$signal<peripherals::$inst> for T

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@ -1,178 +1,17 @@
#![macro_use]
use crate::dma::NoDma;
use crate::gpio::sealed::AFType;
use crate::gpio::sealed::Pin;
use crate::gpio::{AnyPin, NoPin};
use crate::pac::spi;
use crate::peripherals;
use crate::spi::{
ByteOrder, Config, Error, Instance, MisoPin, MosiPin, RxDmaChannel, SckPin, TxDmaChannel,
WordSize,
};
use crate::time::Hertz;
use crate::spi::{Error, Instance, RegsExt, RxDmaChannel, TxDmaChannel, WordSize};
use core::future::Future;
use core::marker::PhantomData;
use core::ptr;
use embassy::util::Unborrow;
use embassy_hal_common::unborrow;
use embassy_traits::spi as traits;
pub use embedded_hal::blocking;
pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
use futures::future::join3;
impl WordSize {
fn dff(&self) -> spi::vals::Dff {
match self {
WordSize::EightBit => spi::vals::Dff::EIGHTBIT,
WordSize::SixteenBit => spi::vals::Dff::SIXTEENBIT,
}
}
}
macro_rules! impl_nopin {
($inst:ident, $signal:ident) => {
impl $signal<peripherals::$inst> for NoPin {}
impl super::sealed::$signal<peripherals::$inst> for NoPin {
fn af_num(&self) -> u8 {
0
}
}
};
}
crate::pac::peripherals!(
(spi, $inst:ident) => {
impl_nopin!($inst, SckPin);
impl_nopin!($inst, MosiPin);
impl_nopin!($inst, MisoPin);
};
);
pub struct Spi<'d, T: Instance, Tx, Rx> {
sck: Option<AnyPin>,
mosi: Option<AnyPin>,
miso: Option<AnyPin>,
txdma: Tx,
rxdma: Rx,
current_word_size: WordSize,
phantom: PhantomData<&'d mut T>,
}
use super::Spi;
impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
pub fn new<F>(
_peri: impl Unborrow<Target = T> + 'd,
sck: impl Unborrow<Target = impl SckPin<T>>,
mosi: impl Unborrow<Target = impl MosiPin<T>>,
miso: impl Unborrow<Target = impl MisoPin<T>>,
txdma: impl Unborrow<Target = Tx>,
rxdma: impl Unborrow<Target = Rx>,
freq: F,
config: Config,
) -> Self
where
F: Into<Hertz>,
{
unborrow!(sck, mosi, miso, txdma, rxdma);
let sck_af = sck.af_num();
let mosi_af = mosi.af_num();
let miso_af = miso.af_num();
let sck = sck.degrade_optional();
let mosi = mosi.degrade_optional();
let miso = miso.degrade_optional();
unsafe {
sck.as_ref()
.map(|x| x.set_as_af(sck_af, AFType::OutputPushPull));
mosi.as_ref()
.map(|x| x.set_as_af(mosi_af, AFType::OutputPushPull));
miso.as_ref().map(|x| x.set_as_af(miso_af, AFType::Input));
}
unsafe {
T::regs().cr2().modify(|w| {
w.set_ssoe(false);
});
}
let pclk = T::frequency();
let br = Self::compute_baud_rate(pclk, freq.into());
unsafe {
T::enable();
T::reset();
T::regs().cr1().modify(|w| {
w.set_cpha(
match config.mode.phase == Phase::CaptureOnSecondTransition {
true => spi::vals::Cpha::SECONDEDGE,
false => spi::vals::Cpha::FIRSTEDGE,
},
);
w.set_cpol(match config.mode.polarity == Polarity::IdleHigh {
true => spi::vals::Cpol::IDLEHIGH,
false => spi::vals::Cpol::IDLELOW,
});
w.set_mstr(spi::vals::Mstr::MASTER);
w.set_br(spi::vals::Br(br));
w.set_spe(true);
w.set_lsbfirst(match config.byte_order {
ByteOrder::LsbFirst => spi::vals::Lsbfirst::LSBFIRST,
ByteOrder::MsbFirst => spi::vals::Lsbfirst::MSBFIRST,
});
w.set_ssi(true);
w.set_ssm(true);
w.set_crcen(false);
w.set_bidimode(spi::vals::Bidimode::UNIDIRECTIONAL);
if mosi.is_none() {
w.set_rxonly(spi::vals::Rxonly::OUTPUTDISABLED);
}
w.set_dff(WordSize::EightBit.dff())
});
}
Self {
sck,
mosi,
miso,
txdma,
rxdma,
current_word_size: WordSize::EightBit,
phantom: PhantomData,
}
}
fn compute_baud_rate(clocks: Hertz, freq: Hertz) -> u8 {
match clocks.0 / freq.0 {
0 => unreachable!(),
1..=2 => 0b000,
3..=5 => 0b001,
6..=11 => 0b010,
12..=23 => 0b011,
24..=39 => 0b100,
40..=95 => 0b101,
96..=191 => 0b110,
_ => 0b111,
}
}
fn set_word_size(&mut self, word_size: WordSize) {
if self.current_word_size == word_size {
return;
}
unsafe {
T::regs().cr1().modify(|reg| {
reg.set_spe(false);
reg.set_dff(word_size.dff())
});
T::regs().cr1().modify(|reg| {
reg.set_spe(true);
});
self.current_word_size = word_size;
}
}
#[allow(unused)]
async fn write_dma_u8(&mut self, write: &[u8]) -> Result<(), Error>
where
@ -186,7 +25,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
self.set_word_size(WordSize::EightBit);
let request = self.txdma.request();
let dst = T::regs().dr().ptr() as *mut u8;
let dst = T::regs().tx_ptr();
let f = self.txdma.write(request, write, dst);
unsafe {
@ -221,11 +60,11 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
let clock_byte_count = read.len();
let rx_request = self.rxdma.request();
let rx_src = T::regs().dr().ptr() as *mut u8;
let rx_src = T::regs().rx_ptr();
let rx_f = self.rxdma.read(rx_request, rx_src, read);
let tx_request = self.txdma.request();
let tx_dst = T::regs().dr().ptr() as *mut u8;
let tx_dst = T::regs().tx_ptr();
let clock_byte = 0x00;
let tx_f = self
.txdma
@ -274,13 +113,13 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
self.set_word_size(WordSize::EightBit);
let rx_request = self.rxdma.request();
let rx_src = T::regs().dr().ptr() as *mut u8;
let rx_src = T::regs().rx_ptr();
let rx_f = self
.rxdma
.read(rx_request, rx_src, &mut read[0..write.len()]);
let tx_request = self.txdma.request();
let tx_dst = T::regs().dr().ptr() as *mut u8;
let tx_dst = T::regs().tx_ptr();
let tx_f = self.txdma.write(tx_request, write, tx_dst);
unsafe {
@ -316,16 +155,6 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
}
}
impl<'d, T: Instance, Tx, Rx> Drop for Spi<'d, T, Tx, Rx> {
fn drop(&mut self) {
unsafe {
self.sck.as_ref().map(|x| x.set_as_analog());
self.mosi.as_ref().map(|x| x.set_as_analog());
self.miso.as_ref().map(|x| x.set_as_analog());
}
}
}
impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u8> for Spi<'d, T, NoDma, NoDma> {
type Error = Error;
@ -452,8 +281,7 @@ fn write_word<W: Word>(regs: &'static crate::pac::spi::Spi, word: W) -> Result<(
}
if sr.txe() {
unsafe {
let dr = regs.dr().ptr() as *mut W;
ptr::write_volatile(dr, word);
ptr::write_volatile(regs.tx_ptr(), word);
}
return Ok(());
}
@ -479,8 +307,7 @@ fn read_word<W: Word>(regs: &'static crate::pac::spi::Spi) -> Result<W, Error> {
}
if sr.rxne() {
unsafe {
let dr = regs.dr().ptr() as *const W;
return Ok(ptr::read_volatile(dr));
return Ok(ptr::read_volatile(regs.rx_ptr()));
}
}
}

View File

@ -1,161 +1,16 @@
#![macro_use]
use crate::dma::NoDma;
use crate::gpio::sealed::Pin;
use crate::gpio::AnyPin;
use crate::pac::spi;
use crate::spi::{
ByteOrder, Config, Error, Instance, MisoPin, MosiPin, RxDmaChannel, SckPin, TxDmaChannel,
WordSize,
};
use crate::time::Hertz;
use crate::spi::{Error, Instance, RegsExt, RxDmaChannel, TxDmaChannel, WordSize};
use core::future::Future;
use core::marker::PhantomData;
use core::ptr;
use embassy::util::Unborrow;
use embassy_hal_common::unborrow;
use embassy_traits::spi as traits;
pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
use futures::future::{join, join3};
impl WordSize {
fn ds(&self) -> spi::vals::Ds {
match self {
WordSize::EightBit => spi::vals::Ds::EIGHTBIT,
WordSize::SixteenBit => spi::vals::Ds::SIXTEENBIT,
}
}
fn frxth(&self) -> spi::vals::Frxth {
match self {
WordSize::EightBit => spi::vals::Frxth::QUARTER,
WordSize::SixteenBit => spi::vals::Frxth::HALF,
}
}
}
pub struct Spi<'d, T: Instance, Tx, Rx> {
sck: Option<AnyPin>,
mosi: Option<AnyPin>,
miso: Option<AnyPin>,
txdma: Tx,
rxdma: Rx,
phantom: PhantomData<&'d mut T>,
}
use super::Spi;
impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
pub fn new<F>(
_peri: impl Unborrow<Target = T> + 'd,
sck: impl Unborrow<Target = impl SckPin<T>>,
mosi: impl Unborrow<Target = impl MosiPin<T>>,
miso: impl Unborrow<Target = impl MisoPin<T>>,
txdma: impl Unborrow<Target = Tx>,
rxdma: impl Unborrow<Target = Rx>,
freq: F,
config: Config,
) -> Self
where
F: Into<Hertz>,
{
unborrow!(sck, mosi, miso, txdma, rxdma);
let sck_af = sck.af_num();
let mosi_af = mosi.af_num();
let miso_af = miso.af_num();
let sck = sck.degrade_optional();
let mosi = mosi.degrade_optional();
let miso = miso.degrade_optional();
unsafe {
sck.as_ref().map(|x| {
x.set_as_af(sck_af, crate::gpio::sealed::AFType::OutputPushPull);
x.set_speed(crate::gpio::Speed::VeryHigh);
});
mosi.as_ref().map(|x| {
x.set_as_af(mosi_af, crate::gpio::sealed::AFType::OutputPushPull);
x.set_speed(crate::gpio::Speed::VeryHigh);
});
miso.as_ref().map(|x| {
x.set_as_af(miso_af, crate::gpio::sealed::AFType::Input);
x.set_speed(crate::gpio::Speed::VeryHigh);
});
}
let pclk = T::frequency();
let freq = freq.into();
let br = Self::compute_baud_rate(pclk, freq);
unsafe {
T::enable();
T::reset();
T::regs().cr2().modify(|w| {
w.set_ssoe(false);
});
T::regs().cr1().modify(|w| {
w.set_cpha(
match config.mode.phase == Phase::CaptureOnSecondTransition {
true => spi::vals::Cpha::SECONDEDGE,
false => spi::vals::Cpha::FIRSTEDGE,
},
);
w.set_cpol(match config.mode.polarity == Polarity::IdleHigh {
true => spi::vals::Cpol::IDLEHIGH,
false => spi::vals::Cpol::IDLELOW,
});
w.set_mstr(spi::vals::Mstr::MASTER);
w.set_br(spi::vals::Br(br));
w.set_lsbfirst(match config.byte_order {
ByteOrder::LsbFirst => spi::vals::Lsbfirst::LSBFIRST,
ByteOrder::MsbFirst => spi::vals::Lsbfirst::MSBFIRST,
});
w.set_ssi(true);
w.set_ssm(true);
w.set_crcen(false);
w.set_bidimode(spi::vals::Bidimode::UNIDIRECTIONAL);
w.set_spe(true);
});
}
Self {
sck,
mosi,
miso,
txdma,
rxdma,
phantom: PhantomData,
}
}
fn compute_baud_rate(clocks: Hertz, freq: Hertz) -> u8 {
match clocks.0 / freq.0 {
0 => unreachable!(),
1..=2 => 0b000,
3..=5 => 0b001,
6..=11 => 0b010,
12..=23 => 0b011,
24..=39 => 0b100,
40..=95 => 0b101,
96..=191 => 0b110,
_ => 0b111,
}
}
fn set_word_size(word_size: WordSize) {
unsafe {
T::regs().cr1().modify(|w| {
w.set_spe(false);
});
T::regs().cr2().modify(|w| {
w.set_frxth(word_size.frxth());
w.set_ds(word_size.ds());
});
T::regs().cr1().modify(|w| {
w.set_spe(true);
});
}
}
#[allow(unused)]
async fn write_dma_u8(&mut self, write: &[u8]) -> Result<(), Error>
where
@ -166,10 +21,10 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
w.set_spe(false);
});
}
Self::set_word_size(WordSize::EightBit);
self.set_word_size(WordSize::EightBit);
let request = self.txdma.request();
let dst = T::regs().dr().ptr() as *mut u8;
let dst = T::regs().tx_ptr();
let f = self.txdma.write(request, write, dst);
unsafe {
@ -208,16 +63,16 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
reg.set_rxdmaen(true);
});
}
Self::set_word_size(WordSize::EightBit);
self.set_word_size(WordSize::EightBit);
let clock_byte_count = read.len();
let rx_request = self.rxdma.request();
let rx_src = T::regs().dr().ptr() as *mut u8;
let rx_src = T::regs().rx_ptr();
let rx_f = self.rxdma.read(rx_request, rx_src, read);
let tx_request = self.txdma.request();
let tx_dst = T::regs().dr().ptr() as *mut u8;
let tx_dst = T::regs().tx_ptr();
let clock_byte = 0x00;
let tx_f = self
.txdma
@ -268,16 +123,16 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
let _ = T::regs().dr().read();
}
}
Self::set_word_size(WordSize::EightBit);
self.set_word_size(WordSize::EightBit);
let rx_request = self.rxdma.request();
let rx_src = T::regs().dr().ptr() as *mut u8;
let rx_src = T::regs().rx_ptr();
let rx_f = self
.rxdma
.read(rx_request, rx_src, &mut read[0..write.len()]);
let tx_request = self.txdma.request();
let tx_dst = T::regs().dr().ptr() as *mut u8;
let tx_dst = T::regs().tx_ptr();
let tx_f = self.txdma.write(tx_request, write, tx_dst);
unsafe {
@ -319,16 +174,6 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
}
}
impl<'d, T: Instance, Tx, Rx> Drop for Spi<'d, T, Tx, Rx> {
fn drop(&mut self) {
unsafe {
self.sck.as_ref().map(|x| x.set_as_analog());
self.mosi.as_ref().map(|x| x.set_as_analog());
self.miso.as_ref().map(|x| x.set_as_analog());
}
}
}
trait Word {}
impl Word for u8 {}
@ -348,8 +193,7 @@ fn write_word<W: Word>(regs: &'static crate::pac::spi::Spi, word: W) -> Result<(
return Err(Error::Crc);
} else if sr.txe() {
unsafe {
let dr = regs.dr().ptr() as *mut W;
ptr::write_volatile(dr, word);
ptr::write_volatile(regs.tx_ptr(), word);
}
return Ok(());
}
@ -370,8 +214,7 @@ fn read_word<W: Word>(regs: &'static crate::pac::spi::Spi) -> Result<W, Error> {
return Err(Error::Crc);
} else if sr.rxne() {
unsafe {
let dr = regs.dr().ptr() as *const W;
return Ok(ptr::read_volatile(dr));
return Ok(ptr::read_volatile(regs.rx_ptr()));
}
}
}
@ -381,7 +224,7 @@ impl<'d, T: Instance, Rx> embedded_hal::blocking::spi::Write<u8> for Spi<'d, T,
type Error = Error;
fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> {
Self::set_word_size(WordSize::EightBit);
self.set_word_size(WordSize::EightBit);
let regs = T::regs();
for word in words.iter() {
@ -397,7 +240,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T, N
type Error = Error;
fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> {
Self::set_word_size(WordSize::EightBit);
self.set_word_size(WordSize::EightBit);
let regs = T::regs();
for word in words.iter_mut() {
@ -413,7 +256,7 @@ impl<'d, T: Instance, Rx> embedded_hal::blocking::spi::Write<u16> for Spi<'d, T,
type Error = Error;
fn write(&mut self, words: &[u16]) -> Result<(), Self::Error> {
Self::set_word_size(WordSize::SixteenBit);
self.set_word_size(WordSize::SixteenBit);
let regs = T::regs();
for word in words.iter() {
@ -429,7 +272,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u16> for Spi<'d, T,
type Error = Error;
fn transfer<'w>(&mut self, words: &'w mut [u16]) -> Result<&'w [u16], Self::Error> {
Self::set_word_size(WordSize::SixteenBit);
self.set_word_size(WordSize::SixteenBit);
let regs = T::regs();
for word in words.iter_mut() {

View File

@ -1,184 +1,23 @@
#![macro_use]
use crate::dma::NoDma;
use crate::gpio::sealed::Pin;
use crate::gpio::AnyPin;
use crate::pac::spi;
use crate::spi::{
ByteOrder, Config, Error, Instance, MisoPin, MosiPin, RxDmaChannel, SckPin, TxDmaChannel,
WordSize,
};
use crate::time::Hertz;
use crate::spi::{Error, Instance, RegsExt, RxDmaChannel, TxDmaChannel, WordSize};
use core::future::Future;
use core::marker::PhantomData;
use core::ptr;
use embassy::util::Unborrow;
use embassy_hal_common::unborrow;
use embassy_traits::spi as traits;
pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
use futures::future::join3;
impl WordSize {
fn dsize(&self) -> u8 {
match self {
WordSize::EightBit => 0b0111,
WordSize::SixteenBit => 0b1111,
}
}
fn _frxth(&self) -> spi::vals::Fthlv {
match self {
WordSize::EightBit => spi::vals::Fthlv::ONEFRAME,
WordSize::SixteenBit => spi::vals::Fthlv::ONEFRAME,
}
}
}
#[allow(unused)]
pub struct Spi<'d, T: Instance, Tx = NoDma, Rx = NoDma> {
sck: Option<AnyPin>,
mosi: Option<AnyPin>,
miso: Option<AnyPin>,
txdma: Tx,
rxdma: Rx,
phantom: PhantomData<&'d mut T>,
}
use super::Spi;
impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
pub fn new<F>(
_peri: impl Unborrow<Target = T> + 'd,
sck: impl Unborrow<Target = impl SckPin<T>>,
mosi: impl Unborrow<Target = impl MosiPin<T>>,
miso: impl Unborrow<Target = impl MisoPin<T>>,
txdma: impl Unborrow<Target = Tx>,
rxdma: impl Unborrow<Target = Rx>,
freq: F,
config: Config,
) -> Self
where
F: Into<Hertz>,
{
unborrow!(sck, mosi, miso, txdma, rxdma);
let sck_af = sck.af_num();
let mosi_af = mosi.af_num();
let miso_af = miso.af_num();
let sck = sck.degrade_optional();
let mosi = mosi.degrade_optional();
let miso = miso.degrade_optional();
unsafe {
sck.as_ref().map(|x| {
x.set_as_af(sck_af, crate::gpio::sealed::AFType::OutputPushPull);
x.set_speed(crate::gpio::Speed::VeryHigh);
});
mosi.as_ref().map(|x| {
x.set_as_af(mosi_af, crate::gpio::sealed::AFType::OutputPushPull);
x.set_speed(crate::gpio::Speed::VeryHigh);
});
miso.as_ref().map(|x| {
x.set_as_af(miso_af, crate::gpio::sealed::AFType::Input);
x.set_speed(crate::gpio::Speed::VeryHigh);
});
}
let pclk = T::frequency();
let br = Self::compute_baud_rate(pclk, freq.into());
unsafe {
T::enable();
T::reset();
T::regs().ifcr().write(|w| w.0 = 0xffff_ffff);
T::regs().cfg2().modify(|w| {
//w.set_ssoe(true);
w.set_ssoe(false);
w.set_cpha(
match config.mode.phase == Phase::CaptureOnSecondTransition {
true => spi::vals::Cpha::SECONDEDGE,
false => spi::vals::Cpha::FIRSTEDGE,
},
);
w.set_cpol(match config.mode.polarity == Polarity::IdleHigh {
true => spi::vals::Cpol::IDLEHIGH,
false => spi::vals::Cpol::IDLELOW,
});
w.set_lsbfrst(match config.byte_order {
ByteOrder::LsbFirst => spi::vals::Lsbfrst::LSBFIRST,
ByteOrder::MsbFirst => spi::vals::Lsbfrst::MSBFIRST,
});
w.set_ssm(true);
w.set_master(spi::vals::Master::MASTER);
w.set_comm(spi::vals::Comm::FULLDUPLEX);
w.set_ssom(spi::vals::Ssom::ASSERTED);
w.set_midi(0);
w.set_mssi(0);
w.set_afcntr(spi::vals::Afcntr::CONTROLLED);
w.set_ssiop(spi::vals::Ssiop::ACTIVEHIGH);
});
T::regs().cfg1().modify(|w| {
w.set_crcen(false);
w.set_mbr(spi::vals::Mbr(br));
w.set_dsize(WordSize::EightBit.dsize());
});
T::regs().cr2().modify(|w| {
w.set_tsize(0);
w.set_tser(0);
});
T::regs().cr1().modify(|w| {
w.set_ssi(false);
w.set_spe(true);
});
}
Self {
sck,
mosi,
miso,
txdma,
rxdma,
phantom: PhantomData,
}
}
fn compute_baud_rate(clocks: Hertz, freq: Hertz) -> u8 {
match clocks.0 / freq.0 {
0 => unreachable!(),
1..=2 => 0b000,
3..=5 => 0b001,
6..=11 => 0b010,
12..=23 => 0b011,
24..=39 => 0b100,
40..=95 => 0b101,
96..=191 => 0b110,
_ => 0b111,
}
}
fn set_word_size(word_size: WordSize) {
unsafe {
T::regs().cr1().modify(|w| {
w.set_csusp(true);
});
while T::regs().sr().read().eot() {}
T::regs().cr1().modify(|w| {
w.set_spe(false);
});
T::regs().cfg1().modify(|w| {
w.set_dsize(word_size.dsize());
});
T::regs().cr1().modify(|w| {
w.set_csusp(false);
w.set_spe(true);
});
}
}
#[allow(unused)]
async fn write_dma_u8(&mut self, write: &[u8]) -> Result<(), Error>
where
Tx: TxDmaChannel<T>,
{
Self::set_word_size(WordSize::EightBit);
self.set_word_size(WordSize::EightBit);
unsafe {
T::regs().cr1().modify(|w| {
w.set_spe(false);
@ -186,7 +25,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
}
let request = self.txdma.request();
let dst = T::regs().txdr().ptr() as *mut u8;
let dst = T::regs().tx_ptr();
let f = self.txdma.write(request, write, dst);
unsafe {
@ -220,7 +59,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
Tx: TxDmaChannel<T>,
Rx: RxDmaChannel<T>,
{
Self::set_word_size(WordSize::EightBit);
self.set_word_size(WordSize::EightBit);
unsafe {
T::regs().cr1().modify(|w| {
w.set_spe(false);
@ -233,11 +72,11 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
let clock_byte_count = read.len();
let rx_request = self.rxdma.request();
let rx_src = T::regs().rxdr().ptr() as *mut u8;
let rx_src = T::regs().rx_ptr();
let rx_f = self.rxdma.read(rx_request, rx_src, read);
let tx_request = self.txdma.request();
let tx_dst = T::regs().txdr().ptr() as *mut u8;
let tx_dst = T::regs().tx_ptr();
let clock_byte = 0x00;
let tx_f = self
.txdma
@ -276,7 +115,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
{
assert!(read.len() >= write.len());
Self::set_word_size(WordSize::EightBit);
self.set_word_size(WordSize::EightBit);
unsafe {
T::regs().cr1().modify(|w| {
w.set_spe(false);
@ -292,13 +131,13 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
}
let rx_request = self.rxdma.request();
let rx_src = T::regs().rxdr().ptr() as *mut u8;
let rx_src = T::regs().rx_ptr();
let rx_f = self
.rxdma
.read(rx_request, rx_src, &mut read[0..write.len()]);
let tx_request = self.txdma.request();
let tx_dst = T::regs().txdr().ptr() as *mut u8;
let tx_dst = T::regs().tx_ptr();
let tx_f = self.txdma.write(tx_request, write, tx_dst);
unsafe {
@ -338,21 +177,11 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
}
}
impl<'d, T: Instance, Tx, Rx> Drop for Spi<'d, T, Tx, Rx> {
fn drop(&mut self) {
unsafe {
self.sck.as_ref().map(|x| x.set_as_analog());
self.mosi.as_ref().map(|x| x.set_as_analog());
self.miso.as_ref().map(|x| x.set_as_analog());
}
}
}
impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u8> for Spi<'d, T, NoDma> {
impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u8> for Spi<'d, T, NoDma, NoDma> {
type Error = Error;
fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> {
Self::set_word_size(WordSize::EightBit);
self.set_word_size(WordSize::EightBit);
let regs = T::regs();
for word in words.iter() {
@ -360,8 +189,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u8> for Spi<'d, T, NoDm
// spin
}
unsafe {
let txdr = regs.txdr().ptr() as *mut u8;
ptr::write_volatile(txdr, *word);
ptr::write_volatile(regs.tx_ptr(), *word);
regs.cr1().modify(|reg| reg.set_cstart(true));
}
loop {
@ -382,9 +210,8 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u8> for Spi<'d, T, NoDm
break;
}
unsafe {
let rxdr = regs.rxdr().ptr() as *const u8;
// discard read to prevent pverrun.
let _ = ptr::read_volatile(rxdr);
let _: u8 = ptr::read_volatile(T::regs().rx_ptr());
}
}
@ -396,11 +223,11 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u8> for Spi<'d, T, NoDm
}
}
impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T, NoDma> {
impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T, NoDma, NoDma> {
type Error = Error;
fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> {
Self::set_word_size(WordSize::EightBit);
self.set_word_size(WordSize::EightBit);
let regs = T::regs();
for word in words.iter_mut() {
@ -413,8 +240,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T, N
// spin
}
unsafe {
let txdr = regs.txdr().ptr() as *mut u8;
ptr::write_volatile(txdr, *word);
ptr::write_volatile(T::regs().tx_ptr(), *word);
regs.cr1().modify(|reg| reg.set_cstart(true));
}
loop {
@ -434,8 +260,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T, N
}
}
unsafe {
let rxdr = regs.rxdr().ptr() as *const u8;
*word = ptr::read_volatile(rxdr);
*word = ptr::read_volatile(T::regs().rx_ptr());
}
let sr = unsafe { regs.sr().read() };
if sr.tifre() {
@ -453,11 +278,11 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T, N
}
}
impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u16> for Spi<'d, T, NoDma> {
impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u16> for Spi<'d, T, NoDma, NoDma> {
type Error = Error;
fn write(&mut self, words: &[u16]) -> Result<(), Self::Error> {
Self::set_word_size(WordSize::SixteenBit);
self.set_word_size(WordSize::SixteenBit);
let regs = T::regs();
for word in words.iter() {
@ -502,11 +327,11 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u16> for Spi<'d, T, NoD
}
}
impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u16> for Spi<'d, T, NoDma> {
impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u16> for Spi<'d, T, NoDma, NoDma> {
type Error = Error;
fn transfer<'w>(&mut self, words: &'w mut [u16]) -> Result<&'w [u16], Self::Error> {
Self::set_word_size(WordSize::SixteenBit);
self.set_word_size(WordSize::SixteenBit);
let regs = T::regs();
for word in words.iter_mut() {