More work on H7 RCC
This commit is contained in:
Thales Fragoso
@@ -1,27 +1,212 @@
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use core::marker::PhantomData;
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use embassy::util::Unborrow;
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use embassy_extras::unborrow;
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use crate::fmt::assert;
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use crate::pac::peripherals;
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use crate::pac::RCC;
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use crate::time::Hertz;
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mod pll;
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use pll::pll_setup;
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pub use pll::PllConfig;
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const HSI: u32 = 64_000_000; // Hz
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const CSI: u32 = 4_000_000; // Hz
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const HSI48: u32 = 48_000_000; // Hz
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const LSI: u32 = 32_000; // Hz
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const HSI: Hertz = Hertz(64_000_000);
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const CSI: Hertz = Hertz(4_000_000);
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const HSI48: Hertz = Hertz(48_000_000);
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const LSI: Hertz = Hertz(32_000);
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/// Configuration of the core clocks
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#[non_exhaustive]
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#[derive(Default)]
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pub struct Config {
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pub hse: Option<u32>,
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pub hse: Option<Hertz>,
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pub bypass_hse: bool,
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pub sys_ck: Option<u32>,
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pub per_ck: Option<u32>,
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pub hclk: Option<u32>,
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pub pclk1: Option<u32>,
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pub pclk2: Option<u32>,
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pub pclk3: Option<u32>,
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pub pclk4: Option<u32>,
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pub sys_ck: Option<Hertz>,
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pub per_ck: Option<Hertz>,
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rcc_hclk: Option<Hertz>,
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pub hclk: Option<Hertz>,
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pub pclk1: Option<Hertz>,
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pub pclk2: Option<Hertz>,
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pub pclk3: Option<Hertz>,
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pub pclk4: Option<Hertz>,
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pub pll1: PllConfig,
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pub pll2: PllConfig,
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pub pll3: PllConfig,
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pub vos: VoltageScale,
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}
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/// Voltage Scale
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///
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/// Represents the voltage range feeding the CPU core. The maximum core
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/// clock frequency depends on this value.
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#[derive(Copy, Clone, PartialEq)]
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pub enum VoltageScale {
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/// VOS 0 range VCORE 1.26V - 1.40V
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Scale0,
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/// VOS 1 range VCORE 1.15V - 1.26V
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Scale1,
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/// VOS 2 range VCORE 1.05V - 1.15V
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Scale2,
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/// VOS 3 range VCORE 0.95V - 1.05V
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Scale3,
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}
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impl Default for VoltageScale {
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fn default() -> Self {
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Self::Scale1
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}
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}
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pub struct Rcc<'d> {
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inner: PhantomData<&'d ()>,
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config: Config,
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}
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impl<'d> Rcc<'d> {
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pub fn new(_rcc: impl Unborrow<Target = peripherals::RCC> + 'd, config: Config) -> Self {
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Self {
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inner: PhantomData,
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config,
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}
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}
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// TODO: FLASH and PWR
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/// Freeze the core clocks, returning a Core Clocks Distribution
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/// and Reset (CCDR) structure. The actual frequency of the clocks
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/// configured is returned in the `clocks` member of the CCDR
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/// structure.
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///
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/// Note that `freeze` will never result in a clock _faster_ than
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/// that specified. It may result in a clock that is a factor of [1,
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/// 2) slower.
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///
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/// `syscfg` is required to enable the I/O compensation cell.
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///
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/// # Panics
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///
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/// If a clock specification cannot be achieved within the
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/// hardware specification then this function will panic. This
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/// function may also panic if a clock specification can be
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/// achieved, but the mechanism for doing so is not yet
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/// implemented here.
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pub fn freeze(mut self) {
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use crate::pac::rcc::vals::{Ckpersel, Hpre, Hsidiv, Hsion, Lsion, Timpre};
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let srcclk = self.config.hse.unwrap_or(HSI); // Available clocks
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let (sys_ck, sys_use_pll1_p) = self.sys_ck_setup(srcclk);
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// NOTE(unsafe) We have exclusive access to the RCC
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let (pll1_p_ck, pll1_q_ck, pll1_r_ck) =
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unsafe { pll_setup(srcclk.0, &self.config.pll1, 0) };
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let (pll2_p_ck, pll2_q_ck, pll2_r_ck) =
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unsafe { pll_setup(srcclk.0, &self.config.pll2, 1) };
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let (pll3_p_ck, pll3_q_ck, pll3_r_ck) =
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unsafe { pll_setup(srcclk.0, &self.config.pll3, 2) };
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let sys_ck = if sys_use_pll1_p {
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Hertz(pll1_p_ck.unwrap()) // Must have been set by sys_ck_setup
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} else {
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sys_ck
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};
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// NOTE(unsafe) We own the regblock
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unsafe {
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// This routine does not support HSIDIV != 1. To
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// do so it would need to ensure all PLLxON bits are clear
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// before changing the value of HSIDIV
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let cr = RCC.cr().read();
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assert!(cr.hsion() == Hsion::ON);
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assert!(cr.hsidiv() == Hsidiv::DIV1);
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RCC.csr().modify(|w| w.set_lsion(Lsion::ON));
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while !RCC.csr().read().lsirdy() {}
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}
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// per_ck from HSI by default
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let (per_ck, ckpersel) = match (self.config.per_ck == self.config.hse, self.config.per_ck) {
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(true, Some(hse)) => (hse, Ckpersel::HSE), // HSE
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(_, Some(CSI)) => (CSI, Ckpersel::CSI), // CSI
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_ => (HSI, Ckpersel::HSI), // HSI
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};
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// D1 Core Prescaler
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// Set to 1
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let d1cpre_bits = 0;
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let d1cpre_div = 1;
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let sys_d1cpre_ck = sys_ck.0 / d1cpre_div;
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// Timer prescaler selection
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let timpre = Timpre::DEFAULTX2;
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// Refer to part datasheet "General operating conditions"
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// table for (rev V). We do not assert checks for earlier
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// revisions which may have lower limits.
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let (sys_d1cpre_ck_max, rcc_hclk_max, pclk_max) = match self.config.vos {
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VoltageScale::Scale0 => (480_000_000, 240_000_000, 120_000_000),
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VoltageScale::Scale1 => (400_000_000, 200_000_000, 100_000_000),
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VoltageScale::Scale2 => (300_000_000, 150_000_000, 75_000_000),
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_ => (200_000_000, 100_000_000, 50_000_000),
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};
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assert!(sys_d1cpre_ck <= sys_d1cpre_ck_max);
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let rcc_hclk = self
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.config
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.rcc_hclk
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.map(|v| v.0)
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.unwrap_or(sys_d1cpre_ck / 2);
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assert!(rcc_hclk <= rcc_hclk_max);
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// Estimate divisor
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let (hpre_bits, hpre_div) = match (sys_d1cpre_ck + rcc_hclk - 1) / rcc_hclk {
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0 => unreachable!(),
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1 => (Hpre::DIV1, 1),
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2 => (Hpre::DIV2, 2),
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3..=5 => (Hpre::DIV4, 4),
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6..=11 => (Hpre::DIV8, 8),
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12..=39 => (Hpre::DIV16, 16),
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40..=95 => (Hpre::DIV64, 64),
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96..=191 => (Hpre::DIV128, 128),
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192..=383 => (Hpre::DIV256, 256),
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_ => (Hpre::DIV512, 512),
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};
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// Calculate real AXI and AHB clock
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let rcc_hclk = sys_d1cpre_ck / hpre_div;
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assert!(rcc_hclk <= rcc_hclk_max);
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let rcc_aclk = rcc_hclk; // AXI clock is always equal to AHB clock on H7
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todo!()
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}
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/// Setup sys_ck
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/// Returns sys_ck frequency, and a pll1_p_ck
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fn sys_ck_setup(&mut self, srcclk: Hertz) -> (Hertz, bool) {
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// Compare available with wanted clocks
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let sys_ck = self.config.sys_ck.unwrap_or(srcclk);
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if sys_ck != srcclk {
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// The requested system clock is not the immediately available
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// HSE/HSI clock. Perhaps there are other ways of obtaining
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// the requested system clock (such as `HSIDIV`) but we will
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// ignore those for now.
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//
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// Therefore we must use pll1_p_ck
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let pll1_p_ck = match self.config.pll1.p_ck {
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Some(p_ck) => {
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assert!(p_ck == sys_ck,
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"Error: Cannot set pll1_p_ck independently as it must be used to generate sys_ck");
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Some(p_ck)
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}
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None => Some(sys_ck),
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};
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self.config.pll1.p_ck = pll1_p_ck;
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(sys_ck, true)
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} else {
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// sys_ck is derived directly from a source clock
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// (HSE/HSI). pll1_p_ck can be as requested
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(sys_ck, false)
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}
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}
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}
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