stm32/rcc: remove Rcc struct, RccExt trait.
All the RCC configuration is executed in init().
This commit is contained in:
Dario Nieuwenhuis
@ -1,23 +1,11 @@
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use core::marker::PhantomData;
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use embassy::util::Unborrow;
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use crate::pac::{
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flash::vals::Latency,
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rcc::vals::{Hpre, Hsebyp, Pllmul, Pllsrc, Ppre, Prediv, Sw, Usbpre},
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FLASH, RCC,
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};
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use crate::peripherals;
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use crate::pac::flash::vals::Latency;
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use crate::pac::rcc::vals::{Hpre, Hsebyp, Pllmul, Pllsrc, Ppre, Prediv, Sw, Usbpre};
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use crate::pac::{FLASH, RCC};
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use crate::rcc::{set_freqs, Clocks};
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use crate::time::Hertz;
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const HSI: u32 = 8_000_000;
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/// RCC peripheral
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pub struct Rcc<'d> {
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config: Config,
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phantom: PhantomData<&'d mut peripherals::RCC>,
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}
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/// Clocks configutation
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#[non_exhaustive]
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#[derive(Default)]
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@ -55,259 +43,228 @@ struct PllConfig {
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/// Initialize and Set the clock frequencies
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pub(crate) unsafe fn init(config: Config) {
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let r = <peripherals::RCC as embassy::util::Steal>::steal();
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let clocks = Rcc::new(r, config).freeze();
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set_freqs(clocks);
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// Calculate the real System clock, and PLL configuration if applicable
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let (Hertz(sysclk), pll_config) = get_sysclk(&config);
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assert!(sysclk <= 72_000_000);
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// Calculate real AHB clock
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let hclk = config.hclk.map(|h| h.0).unwrap_or(sysclk);
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let (hpre_bits, hpre_div) = match sysclk / hclk {
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0 => unreachable!(),
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1 => (Hpre::DIV1, 1),
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2 => (Hpre::DIV2, 2),
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3..=5 => (Hpre::DIV4, 4),
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6..=11 => (Hpre::DIV8, 8),
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12..=39 => (Hpre::DIV16, 16),
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40..=95 => (Hpre::DIV64, 64),
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96..=191 => (Hpre::DIV128, 128),
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192..=383 => (Hpre::DIV256, 256),
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_ => (Hpre::DIV512, 512),
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};
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let hclk = sysclk / hpre_div;
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assert!(hclk <= 72_000_000);
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// Calculate real APB1 clock
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let pclk1 = config.pclk1.map(|p| p.0).unwrap_or(hclk);
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let (ppre1_bits, ppre1) = match hclk / pclk1 {
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0 => unreachable!(),
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1 => (Ppre::DIV1, 1),
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2 => (Ppre::DIV2, 2),
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3..=5 => (Ppre::DIV4, 4),
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6..=11 => (Ppre::DIV8, 8),
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_ => (Ppre::DIV16, 16),
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};
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let timer_mul1 = if ppre1 == 1 { 1 } else { 2 };
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let pclk1 = hclk / ppre1;
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assert!(pclk1 <= 36_000_000);
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// Calculate real APB2 clock
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let pclk2 = config.pclk2.map(|p| p.0).unwrap_or(hclk);
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let (ppre2_bits, ppre2) = match hclk / pclk2 {
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0 => unreachable!(),
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1 => (Ppre::DIV1, 1),
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2 => (Ppre::DIV2, 2),
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3..=5 => (Ppre::DIV4, 4),
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6..=11 => (Ppre::DIV8, 8),
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_ => (Ppre::DIV16, 16),
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};
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let timer_mul2 = if ppre2 == 1 { 1 } else { 2 };
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let pclk2 = hclk / ppre2;
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assert!(pclk2 <= 72_000_000);
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// Set latency based on HCLK frquency
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FLASH.acr().write(|w| {
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w.set_latency(if hclk <= 24_000_000 {
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Latency::WS0
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} else if hclk <= 48_000_000 {
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Latency::WS1
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} else {
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Latency::WS2
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});
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});
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// Enable HSE
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if config.hse.is_some() {
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RCC.cr().write(|w| {
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w.set_hsebyp(if config.bypass_hse {
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Hsebyp::BYPASSED
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} else {
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Hsebyp::NOTBYPASSED
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});
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// We turn on clock security to switch to HSI when HSE fails
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w.set_csson(true);
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w.set_hseon(true);
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});
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while !RCC.cr().read().hserdy() {}
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}
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// Enable PLL
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if let Some(ref pll_config) = pll_config {
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RCC.cfgr().write(|w| {
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w.set_pllmul(pll_config.pll_mul);
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w.set_pllsrc(pll_config.pll_src);
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});
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if let Some(pll_div) = pll_config.pll_div {
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RCC.cfgr2().write(|w| w.set_prediv(pll_div));
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}
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RCC.cr().modify(|w| w.set_pllon(true));
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while !RCC.cr().read().pllrdy() {}
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}
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if config.pll48 {
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let usb_pre = get_usb_pre(&config, sysclk, pclk1, &pll_config);
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RCC.cfgr().write(|w| {
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w.set_usbpre(usb_pre);
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});
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}
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// Set prescalers
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RCC.cfgr().write(|w| {
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w.set_ppre2(ppre2_bits);
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w.set_ppre1(ppre1_bits);
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w.set_hpre(hpre_bits);
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});
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// Wait for the new prescalers to kick in
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// "The clocks are divided with the new prescaler factor from
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// 1 to 16 AHB cycles after write"
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cortex_m::asm::delay(16);
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RCC.cfgr().write(|w| {
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w.set_sw(match (pll_config, config.hse) {
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(Some(_), _) => Sw::PLL,
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(None, Some(_)) => Sw::HSE,
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(None, None) => Sw::HSI,
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})
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});
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set_freqs(Clocks {
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sys: Hertz(sysclk),
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apb1: Hertz(pclk1),
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apb2: Hertz(pclk2),
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apb1_tim: Hertz(pclk1 * timer_mul1),
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apb2_tim: Hertz(pclk2 * timer_mul2),
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ahb: Hertz(hclk),
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});
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}
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impl<'d> Rcc<'d> {
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pub fn new(_rcc: impl Unborrow<Target = peripherals::RCC> + 'd, config: Config) -> Self {
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Self {
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config,
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phantom: PhantomData,
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#[inline]
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fn get_sysclk(config: &Config) -> (Hertz, Option<PllConfig>) {
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match (config.sysclk, config.hse) {
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(Some(sysclk), Some(hse)) if sysclk == hse => (hse, None),
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(Some(sysclk), None) if sysclk.0 == HSI => (Hertz(HSI), None),
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// If the user selected System clock is different from HSI or HSE
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// we will have to setup PLL clock source
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(Some(sysclk), _) => {
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let (sysclk, pll_config) = calc_pll(config, sysclk);
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(sysclk, Some(pll_config))
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}
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(None, Some(hse)) => (hse, None),
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(None, None) => (Hertz(HSI), None),
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}
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}
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fn freeze(self) -> Clocks {
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// Calculate the real System clock, and PLL configuration if applicable
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let (Hertz(sysclk), pll_config) = self.get_sysclk();
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assert!(sysclk <= 72_000_000);
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// Calculate real AHB clock
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let hclk = self.config.hclk.map(|h| h.0).unwrap_or(sysclk);
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let (hpre_bits, hpre_div) = match sysclk / hclk {
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0 => unreachable!(),
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1 => (Hpre::DIV1, 1),
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2 => (Hpre::DIV2, 2),
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3..=5 => (Hpre::DIV4, 4),
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6..=11 => (Hpre::DIV8, 8),
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12..=39 => (Hpre::DIV16, 16),
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40..=95 => (Hpre::DIV64, 64),
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96..=191 => (Hpre::DIV128, 128),
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192..=383 => (Hpre::DIV256, 256),
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_ => (Hpre::DIV512, 512),
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};
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let hclk = sysclk / hpre_div;
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assert!(hclk <= 72_000_000);
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// Calculate real APB1 clock
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let pclk1 = self.config.pclk1.map(|p| p.0).unwrap_or(hclk);
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let (ppre1_bits, ppre1) = match hclk / pclk1 {
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0 => unreachable!(),
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1 => (Ppre::DIV1, 1),
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2 => (Ppre::DIV2, 2),
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3..=5 => (Ppre::DIV4, 4),
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6..=11 => (Ppre::DIV8, 8),
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_ => (Ppre::DIV16, 16),
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};
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let timer_mul1 = if ppre1 == 1 { 1 } else { 2 };
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let pclk1 = hclk / ppre1;
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assert!(pclk1 <= 36_000_000);
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// Calculate real APB2 clock
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let pclk2 = self.config.pclk2.map(|p| p.0).unwrap_or(hclk);
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let (ppre2_bits, ppre2) = match hclk / pclk2 {
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0 => unreachable!(),
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1 => (Ppre::DIV1, 1),
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2 => (Ppre::DIV2, 2),
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3..=5 => (Ppre::DIV4, 4),
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6..=11 => (Ppre::DIV8, 8),
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_ => (Ppre::DIV16, 16),
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};
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let timer_mul2 = if ppre2 == 1 { 1 } else { 2 };
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let pclk2 = hclk / ppre2;
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assert!(pclk2 <= 72_000_000);
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// Set latency based on HCLK frquency
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// NOTE(safety) Atomic write
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unsafe {
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FLASH.acr().write(|w| {
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w.set_latency(if hclk <= 24_000_000 {
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Latency::WS0
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} else if hclk <= 48_000_000 {
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Latency::WS1
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#[inline]
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fn calc_pll(config: &Config, Hertz(sysclk): Hertz) -> (Hertz, PllConfig) {
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// Calculates the Multiplier and the Divisor to arrive at
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// the required System clock from PLL source frequency
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let get_mul_div = |sysclk, pllsrcclk| {
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let common_div = gcd(sysclk, pllsrcclk);
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let mut multiplier = sysclk / common_div;
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let mut divisor = pllsrcclk / common_div;
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// Minimum PLL multiplier is two
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if multiplier == 1 {
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multiplier *= 2;
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divisor *= 2;
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}
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assert!(multiplier <= 16);
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assert!(divisor <= 16);
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(multiplier, divisor)
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};
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// Based on the source of Pll, we calculate the actual system clock
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// frequency, PLL's source identifier, multiplier and divisor
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let (act_sysclk, pll_src, pll_mul, pll_div) = match config.hse {
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Some(Hertz(hse)) => {
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let (multiplier, divisor) = get_mul_div(sysclk, hse);
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(
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Hertz((hse / divisor) * multiplier),
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Pllsrc::HSE_DIV_PREDIV,
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into_pll_mul(multiplier),
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Some(into_pre_div(divisor)),
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)
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}
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None => {
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cfg_if::cfg_if! {
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// For some chips PREDIV is always two, and cannot be changed
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if #[cfg(any(
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feature="stm32f302xd", feature="stm32f302xe", feature="stm32f303xd",
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feature="stm32f303xe", feature="stm32f398xe"
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))] {
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let (multiplier, divisor) = get_mul_div(sysclk, HSI);
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(
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Hertz((hse / divisor) * multiplier),
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Pllsrc::HSI_DIV_PREDIV,
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into_pll_mul(multiplier),
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Some(into_pre_div(divisor)),
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)
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} else {
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Latency::WS2
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});
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})
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}
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// Enable HSE
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if self.config.hse.is_some() {
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// NOTE(unsafe) We own the peripheral block
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unsafe {
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RCC.cr().write(|w| {
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w.set_hsebyp(if self.config.bypass_hse {
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Hsebyp::BYPASSED
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} else {
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Hsebyp::NOTBYPASSED
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});
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// We turn on clock security to switch to HSI when HSE fails
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w.set_csson(true);
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w.set_hseon(true);
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});
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while !RCC.cr().read().hserdy() {}
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}
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}
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// Enable PLL
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if let Some(ref pll_config) = pll_config {
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// NOTE(unsafe) We own the peripheral block
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unsafe {
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RCC.cfgr().write(|w| {
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w.set_pllmul(pll_config.pll_mul);
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w.set_pllsrc(pll_config.pll_src);
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});
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if let Some(pll_div) = pll_config.pll_div {
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RCC.cfgr2().write(|w| w.set_prediv(pll_div));
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}
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RCC.cr().modify(|w| w.set_pllon(true));
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while !RCC.cr().read().pllrdy() {}
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}
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}
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if self.config.pll48 {
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let usb_pre = self.get_usb_pre(sysclk, pclk1, &pll_config);
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// NOTE(unsafe) We own the peripheral block
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unsafe {
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RCC.cfgr().write(|w| {
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w.set_usbpre(usb_pre);
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});
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}
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}
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// Set prescalers
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unsafe {
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// NOTE(unsafe) We own the peripheral block
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RCC.cfgr().write(|w| {
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w.set_ppre2(ppre2_bits);
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w.set_ppre1(ppre1_bits);
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w.set_hpre(hpre_bits);
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});
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// Wait for the new prescalers to kick in
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// "The clocks are divided with the new prescaler factor from
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// 1 to 16 AHB cycles after write"
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cortex_m::asm::delay(16);
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// NOTE(unsafe) We own the peripheral block
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RCC.cfgr().write(|w| {
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w.set_sw(match (pll_config, self.config.hse) {
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(Some(_), _) => Sw::PLL,
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(None, Some(_)) => Sw::HSE,
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(None, None) => Sw::HSI,
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})
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});
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}
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Clocks {
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sys: Hertz(sysclk),
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apb1: Hertz(pclk1),
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apb2: Hertz(pclk2),
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apb1_tim: Hertz(pclk1 * timer_mul1),
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apb2_tim: Hertz(pclk2 * timer_mul2),
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ahb: Hertz(hclk),
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}
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}
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#[inline]
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fn get_sysclk(&self) -> (Hertz, Option<PllConfig>) {
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match (self.config.sysclk, self.config.hse) {
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(Some(sysclk), Some(hse)) if sysclk == hse => (hse, None),
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(Some(sysclk), None) if sysclk.0 == HSI => (Hertz(HSI), None),
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// If the user selected System clock is different from HSI or HSE
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// we will have to setup PLL clock source
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(Some(sysclk), _) => {
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let (sysclk, pll_config) = self.calc_pll(sysclk);
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(sysclk, Some(pll_config))
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}
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(None, Some(hse)) => (hse, None),
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(None, None) => (Hertz(HSI), None),
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}
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}
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#[inline]
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fn calc_pll(&self, Hertz(sysclk): Hertz) -> (Hertz, PllConfig) {
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// Calculates the Multiplier and the Divisor to arrive at
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// the required System clock from PLL source frequency
|
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let get_mul_div = |sysclk, pllsrcclk| {
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let common_div = gcd(sysclk, pllsrcclk);
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let mut multiplier = sysclk / common_div;
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let mut divisor = pllsrcclk / common_div;
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// Minimum PLL multiplier is two
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if multiplier == 1 {
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multiplier *= 2;
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divisor *= 2;
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}
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assert!(multiplier <= 16);
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assert!(divisor <= 16);
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(multiplier, divisor)
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};
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// Based on the source of Pll, we calculate the actual system clock
|
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// frequency, PLL's source identifier, multiplier and divisor
|
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let (act_sysclk, pll_src, pll_mul, pll_div) = match self.config.hse {
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Some(Hertz(hse)) => {
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let (multiplier, divisor) = get_mul_div(sysclk, hse);
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(
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Hertz((hse / divisor) * multiplier),
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Pllsrc::HSE_DIV_PREDIV,
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into_pll_mul(multiplier),
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Some(into_pre_div(divisor)),
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)
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}
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None => {
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cfg_if::cfg_if! {
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// For some chips PREDIV is always two, and cannot be changed
|
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if #[cfg(any(
|
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feature="stm32f302xd", feature="stm32f302xe", feature="stm32f303xd",
|
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feature="stm32f303xe", feature="stm32f398xe"
|
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))] {
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let (multiplier, divisor) = get_mul_div(sysclk, HSI);
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(
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Hertz((hse / divisor) * multiplier),
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Pllsrc::HSI_DIV_PREDIV,
|
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into_pll_mul(multiplier),
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Some(into_pre_div(divisor)),
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)
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} else {
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let pllsrcclk = HSI / 2;
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let multiplier = sysclk / pllsrcclk;
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assert!(multiplier <= 16);
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(
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Hertz(pllsrcclk * multiplier),
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Pllsrc::HSI_DIV2,
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into_pll_mul(multiplier),
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None,
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)
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}
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let pllsrcclk = HSI / 2;
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let multiplier = sysclk / pllsrcclk;
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assert!(multiplier <= 16);
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(
|
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Hertz(pllsrcclk * multiplier),
|
||||
Pllsrc::HSI_DIV2,
|
||||
into_pll_mul(multiplier),
|
||||
None,
|
||||
)
|
||||
}
|
||||
}
|
||||
};
|
||||
(
|
||||
act_sysclk,
|
||||
PllConfig {
|
||||
pll_src,
|
||||
pll_mul,
|
||||
pll_div,
|
||||
},
|
||||
)
|
||||
}
|
||||
}
|
||||
};
|
||||
(
|
||||
act_sysclk,
|
||||
PllConfig {
|
||||
pll_src,
|
||||
pll_mul,
|
||||
pll_div,
|
||||
},
|
||||
)
|
||||
}
|
||||
|
||||
#[inline]
|
||||
fn get_usb_pre(&self, sysclk: u32, pclk1: u32, pll_config: &Option<PllConfig>) -> Usbpre {
|
||||
cfg_if::cfg_if! {
|
||||
// Some chips do not have USB
|
||||
if #[cfg(any(stm32f301, stm32f318, stm32f334))] {
|
||||
panic!("USB clock not supported by the chip");
|
||||
} else {
|
||||
let usb_ok = self.config.hse.is_some() && pll_config.is_some() && (pclk1 >= 10_000_000);
|
||||
match (usb_ok, sysclk) {
|
||||
(true, 72_000_000) => Usbpre::DIV1_5,
|
||||
(true, 48_000_000) => Usbpre::DIV1,
|
||||
_ => panic!(
|
||||
"USB clock is only valid if the PLL output frequency is either 48MHz or 72MHz"
|
||||
),
|
||||
}
|
||||
#[inline]
|
||||
fn get_usb_pre(config: &Config, sysclk: u32, pclk1: u32, pll_config: &Option<PllConfig>) -> Usbpre {
|
||||
cfg_if::cfg_if! {
|
||||
// Some chips do not have USB
|
||||
if #[cfg(any(stm32f301, stm32f318, stm32f334))] {
|
||||
panic!("USB clock not supported by the chip");
|
||||
} else {
|
||||
let usb_ok = config.hse.is_some() && pll_config.is_some() && (pclk1 >= 10_000_000);
|
||||
match (usb_ok, sysclk) {
|
||||
(true, 72_000_000) => Usbpre::DIV1_5,
|
||||
(true, 48_000_000) => Usbpre::DIV1,
|
||||
_ => panic!(
|
||||
"USB clock is only valid if the PLL output frequency is either 48MHz or 72MHz"
|
||||
),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user