Add split method to UarteWithIdle
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@ -554,10 +554,8 @@ pub(in crate) fn drop_tx_rx(r: &pac::uarte0::RegisterBlock, s: &sealed::State) {
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/// Interface to an UARTE peripheral that uses an additional timer and two PPI channels,
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/// Interface to an UARTE peripheral that uses an additional timer and two PPI channels,
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/// allowing it to implement the ReadUntilIdle trait.
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/// allowing it to implement the ReadUntilIdle trait.
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pub struct UarteWithIdle<'d, U: Instance, T: TimerInstance> {
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pub struct UarteWithIdle<'d, U: Instance, T: TimerInstance> {
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uarte: Uarte<'d, U>,
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tx: UarteTx<'d, U>,
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timer: Timer<'d, T>,
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rx: UarteRxWithIdle<'d, U, T>,
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ppi_ch1: Ppi<'d, AnyConfigurableChannel, 1, 2>,
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_ppi_ch2: Ppi<'d, AnyConfigurableChannel, 1, 1>,
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}
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}
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impl<'d, U: Instance, T: TimerInstance> UarteWithIdle<'d, U, T> {
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impl<'d, U: Instance, T: TimerInstance> UarteWithIdle<'d, U, T> {
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@ -628,7 +626,8 @@ impl<'d, U: Instance, T: TimerInstance> UarteWithIdle<'d, U, T> {
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config: Config,
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config: Config,
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) -> Self {
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) -> Self {
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let baudrate = config.baudrate;
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let baudrate = config.baudrate;
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let uarte = Uarte::new_inner(uarte, irq, rxd, txd, cts, rts, config);
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let (tx, rx) = Uarte::new_inner(uarte, irq, rxd, txd, cts, rts, config).split();
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let mut timer = Timer::new(timer);
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let mut timer = Timer::new(timer);
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unborrow!(ppi_ch1, ppi_ch2);
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unborrow!(ppi_ch1, ppi_ch2);
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@ -664,29 +663,64 @@ impl<'d, U: Instance, T: TimerInstance> UarteWithIdle<'d, U, T> {
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ppi_ch2.enable();
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ppi_ch2.enable();
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Self {
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Self {
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uarte,
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tx,
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timer,
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rx: UarteRxWithIdle {
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ppi_ch1: ppi_ch1,
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rx,
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_ppi_ch2: ppi_ch2,
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timer,
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ppi_ch1: ppi_ch1,
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_ppi_ch2: ppi_ch2,
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},
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}
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}
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}
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}
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/// Split the Uarte into a transmitter and receiver, which is
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/// particuarly useful when having two tasks correlating to
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/// transmitting and receiving.
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pub fn split(self) -> (UarteTx<'d, U>, UarteRxWithIdle<'d, U, T>) {
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(self.tx, self.rx)
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}
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pub async fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
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pub async fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
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self.ppi_ch1.disable();
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self.rx.read(buffer).await
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self.uarte.read(buffer).await
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}
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}
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pub async fn write(&mut self, buffer: &[u8]) -> Result<(), Error> {
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pub async fn write(&mut self, buffer: &[u8]) -> Result<(), Error> {
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self.uarte.write(buffer).await
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self.tx.write(buffer).await
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}
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pub fn blocking_read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
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self.rx.blocking_read(buffer)
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}
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pub fn blocking_write(&mut self, buffer: &[u8]) -> Result<(), Error> {
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self.tx.blocking_write(buffer)
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}
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pub async fn read_until_idle(&mut self, buffer: &mut [u8]) -> Result<usize, Error> {
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self.rx.read_until_idle(buffer).await
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}
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pub fn blocking_read_until_idle(&mut self, buffer: &mut [u8]) -> Result<usize, Error> {
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self.rx.blocking_read_until_idle(buffer)
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}
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}
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pub struct UarteRxWithIdle<'d, U: Instance, T: TimerInstance> {
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rx: UarteRx<'d, U>,
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timer: Timer<'d, T>,
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ppi_ch1: Ppi<'d, AnyConfigurableChannel, 1, 2>,
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_ppi_ch2: Ppi<'d, AnyConfigurableChannel, 1, 1>,
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}
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impl<'d, U: Instance, T: TimerInstance> UarteRxWithIdle<'d, U, T> {
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pub async fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
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self.ppi_ch1.disable();
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self.rx.read(buffer).await
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}
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}
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pub fn blocking_read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
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pub fn blocking_read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
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self.ppi_ch1.disable();
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self.ppi_ch1.disable();
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self.uarte.blocking_read(buffer)
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self.rx.blocking_read(buffer)
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}
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pub fn blocking_write(&mut self, buffer: &[u8]) -> Result<(), Error> {
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self.uarte.blocking_write(buffer)
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}
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}
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pub async fn read_until_idle(&mut self, buffer: &mut [u8]) -> Result<usize, Error> {
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pub async fn read_until_idle(&mut self, buffer: &mut [u8]) -> Result<usize, Error> {
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@ -706,8 +740,6 @@ impl<'d, U: Instance, T: TimerInstance> UarteWithIdle<'d, U, T> {
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self.ppi_ch1.enable();
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self.ppi_ch1.enable();
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let drop = OnDrop::new(|| {
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let drop = OnDrop::new(|| {
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trace!("read drop: stopping");
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self.timer.stop();
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self.timer.stop();
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r.intenclr.write(|w| w.endrx().clear());
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r.intenclr.write(|w| w.endrx().clear());
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@ -715,8 +747,6 @@ impl<'d, U: Instance, T: TimerInstance> UarteWithIdle<'d, U, T> {
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r.tasks_stoprx.write(|w| unsafe { w.bits(1) });
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r.tasks_stoprx.write(|w| unsafe { w.bits(1) });
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while r.events_endrx.read().bits() == 0 {}
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while r.events_endrx.read().bits() == 0 {}
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trace!("read drop: stopped");
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});
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});
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r.rxd.ptr.write(|w| unsafe { w.ptr().bits(ptr as u32) });
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r.rxd.ptr.write(|w| unsafe { w.ptr().bits(ptr as u32) });
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@ -785,7 +815,6 @@ impl<'d, U: Instance, T: TimerInstance> UarteWithIdle<'d, U, T> {
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Ok(n)
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Ok(n)
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}
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}
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}
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}
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pub(crate) mod sealed {
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pub(crate) mod sealed {
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use core::sync::atomic::AtomicU8;
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use core::sync::atomic::AtomicU8;
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