stm32/rcc: extract and combine ahb/apb prescalers
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@ -1,5 +1,6 @@
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use stm32_metapac::PWR;
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pub use super::common::{AHBPrescaler, APBPrescaler};
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use crate::pac::rcc::vals::{Hpre, Msirange, Pllsrc, Ppre, Sw};
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use crate::pac::{FLASH, RCC};
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use crate::rcc::{set_freqs, Clocks};
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@ -71,30 +72,6 @@ pub enum PLLDiv {
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Div4,
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}
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/// AHB prescaler
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#[derive(Clone, Copy, PartialEq)]
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pub enum AHBPrescaler {
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NotDivided,
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Div2,
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Div4,
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Div8,
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Div16,
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Div64,
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Div128,
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Div256,
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Div512,
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}
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/// APB prescaler
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#[derive(Clone, Copy)]
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pub enum APBPrescaler {
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NotDivided,
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Div2,
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Div4,
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Div8,
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Div16,
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}
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/// PLL clock input source
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#[derive(Clone, Copy)]
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pub enum PLLSource {
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@ -202,34 +179,6 @@ impl From<PLLSource> for Pllsrc {
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}
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}
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impl From<APBPrescaler> for Ppre {
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fn from(val: APBPrescaler) -> Ppre {
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match val {
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APBPrescaler::NotDivided => Ppre::DIV1,
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APBPrescaler::Div2 => Ppre::DIV2,
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APBPrescaler::Div4 => Ppre::DIV4,
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APBPrescaler::Div8 => Ppre::DIV8,
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APBPrescaler::Div16 => Ppre::DIV16,
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}
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}
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}
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impl From<AHBPrescaler> for Hpre {
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fn from(val: AHBPrescaler) -> Hpre {
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match val {
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AHBPrescaler::NotDivided => Hpre::DIV1,
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AHBPrescaler::Div2 => Hpre::DIV2,
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AHBPrescaler::Div4 => Hpre::DIV4,
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AHBPrescaler::Div8 => Hpre::DIV8,
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AHBPrescaler::Div16 => Hpre::DIV16,
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AHBPrescaler::Div64 => Hpre::DIV64,
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AHBPrescaler::Div128 => Hpre::DIV128,
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AHBPrescaler::Div256 => Hpre::DIV256,
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AHBPrescaler::Div512 => Hpre::DIV512,
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}
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}
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}
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impl From<MSIRange> for Msirange {
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fn from(val: MSIRange) -> Msirange {
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match val {
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