stm32: move to bind_interrupts
disable lora functionality for now
This commit is contained in:
@ -1,4 +1,5 @@
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use core::future::poll_fn;
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use core::marker::PhantomData;
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use core::task::Poll;
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use embassy_hal_common::{into_ref, PeripheralRef};
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@ -8,7 +9,31 @@ use crate::dma::Transfer;
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use crate::gpio::sealed::AFType;
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use crate::gpio::Speed;
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use crate::interrupt::{Interrupt, InterruptExt};
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use crate::Peripheral;
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use crate::{interrupt, Peripheral};
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/// Interrupt handler.
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pub struct InterruptHandler<T: Instance> {
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_phantom: PhantomData<T>,
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}
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impl<T: Instance> interrupt::Handler<T::Interrupt> for InterruptHandler<T> {
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unsafe fn on_interrupt() {
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let ris = crate::pac::DCMI.ris().read();
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if ris.err_ris() {
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trace!("DCMI IRQ: Error.");
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crate::pac::DCMI.ier().modify(|ier| ier.set_err_ie(false));
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}
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if ris.ovr_ris() {
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trace!("DCMI IRQ: Overrun.");
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crate::pac::DCMI.ier().modify(|ier| ier.set_ovr_ie(false));
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}
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if ris.frame_ris() {
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trace!("DCMI IRQ: Frame captured.");
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crate::pac::DCMI.ier().modify(|ier| ier.set_frame_ie(false));
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}
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STATE.waker.wake();
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}
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}
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/// The level on the VSync pin when the data is not valid on the parallel interface.
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#[derive(Clone, Copy, PartialEq)]
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@ -94,7 +119,7 @@ where
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pub fn new_8bit(
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peri: impl Peripheral<P = T> + 'd,
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dma: impl Peripheral<P = Dma> + 'd,
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
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d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
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d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
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d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
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@ -108,17 +133,17 @@ where
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pixclk: impl Peripheral<P = impl PixClkPin<T>> + 'd,
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config: Config,
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) -> Self {
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into_ref!(peri, dma, irq);
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into_ref!(peri, dma);
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config_pins!(d0, d1, d2, d3, d4, d5, d6, d7);
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config_pins!(v_sync, h_sync, pixclk);
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Self::new_inner(peri, dma, irq, config, false, 0b00)
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Self::new_inner(peri, dma, config, false, 0b00)
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}
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pub fn new_10bit(
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peri: impl Peripheral<P = T> + 'd,
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dma: impl Peripheral<P = Dma> + 'd,
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
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d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
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d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
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d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
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@ -134,17 +159,17 @@ where
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pixclk: impl Peripheral<P = impl PixClkPin<T>> + 'd,
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config: Config,
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) -> Self {
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into_ref!(peri, dma, irq);
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into_ref!(peri, dma);
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config_pins!(d0, d1, d2, d3, d4, d5, d6, d7, d8, d9);
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config_pins!(v_sync, h_sync, pixclk);
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Self::new_inner(peri, dma, irq, config, false, 0b01)
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Self::new_inner(peri, dma, config, false, 0b01)
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}
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pub fn new_12bit(
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peri: impl Peripheral<P = T> + 'd,
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dma: impl Peripheral<P = Dma> + 'd,
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
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d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
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d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
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d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
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@ -162,17 +187,17 @@ where
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pixclk: impl Peripheral<P = impl PixClkPin<T>> + 'd,
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config: Config,
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) -> Self {
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into_ref!(peri, dma, irq);
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into_ref!(peri, dma);
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config_pins!(d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11);
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config_pins!(v_sync, h_sync, pixclk);
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Self::new_inner(peri, dma, irq, config, false, 0b10)
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Self::new_inner(peri, dma, config, false, 0b10)
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}
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pub fn new_14bit(
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peri: impl Peripheral<P = T> + 'd,
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dma: impl Peripheral<P = Dma> + 'd,
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
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d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
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d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
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d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
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@ -192,17 +217,17 @@ where
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pixclk: impl Peripheral<P = impl PixClkPin<T>> + 'd,
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config: Config,
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) -> Self {
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into_ref!(peri, dma, irq);
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into_ref!(peri, dma);
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config_pins!(d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13);
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config_pins!(v_sync, h_sync, pixclk);
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Self::new_inner(peri, dma, irq, config, false, 0b11)
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Self::new_inner(peri, dma, config, false, 0b11)
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}
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pub fn new_es_8bit(
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peri: impl Peripheral<P = T> + 'd,
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dma: impl Peripheral<P = Dma> + 'd,
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
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d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
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d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
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d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
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@ -214,17 +239,17 @@ where
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pixclk: impl Peripheral<P = impl PixClkPin<T>> + 'd,
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config: Config,
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) -> Self {
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into_ref!(peri, dma, irq);
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into_ref!(peri, dma);
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config_pins!(d0, d1, d2, d3, d4, d5, d6, d7);
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config_pins!(pixclk);
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Self::new_inner(peri, dma, irq, config, true, 0b00)
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Self::new_inner(peri, dma, config, true, 0b00)
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}
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pub fn new_es_10bit(
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peri: impl Peripheral<P = T> + 'd,
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dma: impl Peripheral<P = Dma> + 'd,
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
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d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
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d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
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d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
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@ -238,17 +263,17 @@ where
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pixclk: impl Peripheral<P = impl PixClkPin<T>> + 'd,
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config: Config,
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) -> Self {
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into_ref!(peri, dma, irq);
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into_ref!(peri, dma);
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config_pins!(d0, d1, d2, d3, d4, d5, d6, d7, d8, d9);
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config_pins!(pixclk);
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Self::new_inner(peri, dma, irq, config, true, 0b01)
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Self::new_inner(peri, dma, config, true, 0b01)
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}
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pub fn new_es_12bit(
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peri: impl Peripheral<P = T> + 'd,
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dma: impl Peripheral<P = Dma> + 'd,
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
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d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
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d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
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d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
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@ -264,17 +289,17 @@ where
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pixclk: impl Peripheral<P = impl PixClkPin<T>> + 'd,
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config: Config,
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) -> Self {
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into_ref!(peri, dma, irq);
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into_ref!(peri, dma);
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config_pins!(d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11);
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config_pins!(pixclk);
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Self::new_inner(peri, dma, irq, config, true, 0b10)
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Self::new_inner(peri, dma, config, true, 0b10)
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}
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pub fn new_es_14bit(
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peri: impl Peripheral<P = T> + 'd,
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dma: impl Peripheral<P = Dma> + 'd,
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
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d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
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d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
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d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
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@ -292,17 +317,16 @@ where
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pixclk: impl Peripheral<P = impl PixClkPin<T>> + 'd,
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config: Config,
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) -> Self {
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into_ref!(peri, dma, irq);
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into_ref!(peri, dma);
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config_pins!(d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13);
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config_pins!(pixclk);
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Self::new_inner(peri, dma, irq, config, true, 0b11)
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Self::new_inner(peri, dma, config, true, 0b11)
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}
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fn new_inner(
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peri: PeripheralRef<'d, T>,
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dma: PeripheralRef<'d, Dma>,
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irq: PeripheralRef<'d, T::Interrupt>,
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config: Config,
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use_embedded_synchronization: bool,
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edm: u8,
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@ -322,30 +346,12 @@ where
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});
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}
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irq.set_handler(Self::on_interrupt);
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irq.unpend();
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irq.enable();
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unsafe { T::Interrupt::steal() }.unpend();
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unsafe { T::Interrupt::steal() }.enable();
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Self { inner: peri, dma }
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}
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unsafe fn on_interrupt(_: *mut ()) {
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let ris = crate::pac::DCMI.ris().read();
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if ris.err_ris() {
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trace!("DCMI IRQ: Error.");
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crate::pac::DCMI.ier().modify(|ier| ier.set_err_ie(false));
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}
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if ris.ovr_ris() {
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trace!("DCMI IRQ: Overrun.");
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crate::pac::DCMI.ier().modify(|ier| ier.set_ovr_ie(false));
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}
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if ris.frame_ris() {
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trace!("DCMI IRQ: Frame captured.");
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crate::pac::DCMI.ier().modify(|ier| ier.set_frame_ie(false));
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}
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STATE.waker.wake();
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}
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unsafe fn toggle(enable: bool) {
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crate::pac::DCMI.cr().modify(|r| {
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r.set_enable(enable);
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@ -11,7 +11,7 @@ use core::task::Context;
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use embassy_net_driver::{Capabilities, LinkState};
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use embassy_sync::waitqueue::AtomicWaker;
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pub use self::_version::*;
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pub use self::_version::{InterruptHandler, *};
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#[allow(unused)]
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const MTU: usize = 1514;
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@ -5,7 +5,7 @@ mod tx_desc;
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use core::sync::atomic::{fence, Ordering};
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use embassy_cortex_m::interrupt::InterruptExt;
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use embassy_cortex_m::interrupt::{Interrupt, InterruptExt};
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use embassy_hal_common::{into_ref, PeripheralRef};
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use stm32_metapac::eth::vals::{Apcs, Cr, Dm, DmaomrSr, Fes, Ftf, Ifg, MbProgress, Mw, Pbl, Rsf, St, Tsf};
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@ -19,7 +19,30 @@ use crate::pac::AFIO;
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#[cfg(any(eth_v1b, eth_v1c))]
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use crate::pac::SYSCFG;
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use crate::pac::{ETH, RCC};
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use crate::Peripheral;
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use crate::{interrupt, Peripheral};
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/// Interrupt handler.
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pub struct InterruptHandler {}
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impl interrupt::Handler<interrupt::ETH> for InterruptHandler {
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unsafe fn on_interrupt() {
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WAKER.wake();
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// TODO: Check and clear more flags
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unsafe {
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let dma = ETH.ethernet_dma();
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dma.dmasr().modify(|w| {
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w.set_ts(true);
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w.set_rs(true);
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w.set_nis(true);
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});
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// Delay two peripheral's clock
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dma.dmasr().read();
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dma.dmasr().read();
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}
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}
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}
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pub struct Ethernet<'d, T: Instance, P: PHY> {
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_peri: PeripheralRef<'d, T>,
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@ -77,7 +100,7 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
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pub fn new<const TX: usize, const RX: usize>(
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queue: &'d mut PacketQueue<TX, RX>,
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peri: impl Peripheral<P = T> + 'd,
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interrupt: impl Peripheral<P = crate::interrupt::ETH> + 'd,
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_irq: impl interrupt::Binding<interrupt::ETH, InterruptHandler> + 'd,
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ref_clk: impl Peripheral<P = impl RefClkPin<T>> + 'd,
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mdio: impl Peripheral<P = impl MDIOPin<T>> + 'd,
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mdc: impl Peripheral<P = impl MDCPin<T>> + 'd,
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@ -91,7 +114,7 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
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mac_addr: [u8; 6],
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phy_addr: u8,
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) -> Self {
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into_ref!(peri, interrupt, ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
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into_ref!(peri, ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
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unsafe {
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// Enable the necessary Clocks
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@ -244,30 +267,12 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
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P::phy_reset(&mut this);
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P::phy_init(&mut this);
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interrupt.set_handler(Self::on_interrupt);
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interrupt.enable();
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interrupt::ETH::steal().unpend();
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interrupt::ETH::steal().enable();
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this
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}
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}
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fn on_interrupt(_cx: *mut ()) {
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WAKER.wake();
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// TODO: Check and clear more flags
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unsafe {
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let dma = ETH.ethernet_dma();
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dma.dmasr().modify(|w| {
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w.set_ts(true);
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w.set_rs(true);
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w.set_nis(true);
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});
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// Delay two peripheral's clock
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dma.dmasr().read();
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dma.dmasr().read();
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}
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}
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}
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unsafe impl<'d, T: Instance, P: PHY> StationManagement for Ethernet<'d, T, P> {
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|
@ -2,7 +2,7 @@ mod descriptors;
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use core::sync::atomic::{fence, Ordering};
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use embassy_cortex_m::interrupt::InterruptExt;
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use embassy_cortex_m::interrupt::{Interrupt, InterruptExt};
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use embassy_hal_common::{into_ref, PeripheralRef};
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pub(crate) use self::descriptors::{RDes, RDesRing, TDes, TDesRing};
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@ -10,7 +10,30 @@ use super::*;
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use crate::gpio::sealed::{AFType, Pin as _};
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use crate::gpio::{AnyPin, Speed};
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use crate::pac::ETH;
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use crate::Peripheral;
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use crate::{interrupt, Peripheral};
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/// Interrupt handler.
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pub struct InterruptHandler {}
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impl interrupt::Handler<interrupt::ETH> for InterruptHandler {
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unsafe fn on_interrupt() {
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WAKER.wake();
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// TODO: Check and clear more flags
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unsafe {
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let dma = ETH.ethernet_dma();
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dma.dmacsr().modify(|w| {
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w.set_ti(true);
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w.set_ri(true);
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w.set_nis(true);
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});
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// Delay two peripheral's clock
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dma.dmacsr().read();
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dma.dmacsr().read();
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}
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}
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}
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const MTU: usize = 1514; // 14 Ethernet header + 1500 IP packet
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@ -41,7 +64,7 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
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pub fn new<const TX: usize, const RX: usize>(
|
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queue: &'d mut PacketQueue<TX, RX>,
|
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peri: impl Peripheral<P = T> + 'd,
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interrupt: impl Peripheral<P = crate::interrupt::ETH> + 'd,
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_irq: impl interrupt::Binding<interrupt::ETH, InterruptHandler> + 'd,
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ref_clk: impl Peripheral<P = impl RefClkPin<T>> + 'd,
|
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mdio: impl Peripheral<P = impl MDIOPin<T>> + 'd,
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mdc: impl Peripheral<P = impl MDCPin<T>> + 'd,
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@ -55,7 +78,7 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
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mac_addr: [u8; 6],
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phy_addr: u8,
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) -> Self {
|
||||
into_ref!(peri, interrupt, ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
|
||||
into_ref!(peri, ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
|
||||
|
||||
unsafe {
|
||||
// Enable the necessary Clocks
|
||||
@ -215,30 +238,12 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
|
||||
P::phy_reset(&mut this);
|
||||
P::phy_init(&mut this);
|
||||
|
||||
interrupt.set_handler(Self::on_interrupt);
|
||||
interrupt.enable();
|
||||
interrupt::ETH::steal().unpend();
|
||||
interrupt::ETH::steal().enable();
|
||||
|
||||
this
|
||||
}
|
||||
}
|
||||
|
||||
fn on_interrupt(_cx: *mut ()) {
|
||||
WAKER.wake();
|
||||
|
||||
// TODO: Check and clear more flags
|
||||
unsafe {
|
||||
let dma = ETH.ethernet_dma();
|
||||
|
||||
dma.dmacsr().modify(|w| {
|
||||
w.set_ti(true);
|
||||
w.set_ri(true);
|
||||
w.set_nis(true);
|
||||
});
|
||||
// Delay two peripheral's clock
|
||||
dma.dmacsr().read();
|
||||
dma.dmacsr().read();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
unsafe impl<'d, T: Instance, P: PHY> StationManagement for Ethernet<'d, T, P> {
|
||||
|
@ -9,7 +9,16 @@ use crate::gpio::Pull;
|
||||
use crate::i2c::{Error, Instance, SclPin, SdaPin};
|
||||
use crate::pac::i2c;
|
||||
use crate::time::Hertz;
|
||||
use crate::Peripheral;
|
||||
use crate::{interrupt, Peripheral};
|
||||
|
||||
/// Interrupt handler.
|
||||
pub struct InterruptHandler<T: Instance> {
|
||||
_phantom: PhantomData<T>,
|
||||
}
|
||||
|
||||
impl<T: Instance> interrupt::Handler<T::Interrupt> for InterruptHandler<T> {
|
||||
unsafe fn on_interrupt() {}
|
||||
}
|
||||
|
||||
#[non_exhaustive]
|
||||
#[derive(Copy, Clone)]
|
||||
@ -48,7 +57,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
|
||||
_peri: impl Peripheral<P = T> + 'd,
|
||||
scl: impl Peripheral<P = impl SclPin<T>> + 'd,
|
||||
sda: impl Peripheral<P = impl SdaPin<T>> + 'd,
|
||||
_irq: impl Peripheral<P = T::Interrupt> + 'd,
|
||||
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
|
||||
tx_dma: impl Peripheral<P = TXDMA> + 'd,
|
||||
rx_dma: impl Peripheral<P = RXDMA> + 'd,
|
||||
freq: Hertz,
|
||||
|
@ -1,7 +1,9 @@
|
||||
use core::cmp;
|
||||
use core::future::poll_fn;
|
||||
use core::marker::PhantomData;
|
||||
use core::task::Poll;
|
||||
|
||||
use embassy_cortex_m::interrupt::{Interrupt, InterruptExt};
|
||||
use embassy_embedded_hal::SetConfig;
|
||||
use embassy_hal_common::drop::OnDrop;
|
||||
use embassy_hal_common::{into_ref, PeripheralRef};
|
||||
@ -11,10 +13,30 @@ use crate::dma::{NoDma, Transfer};
|
||||
use crate::gpio::sealed::AFType;
|
||||
use crate::gpio::Pull;
|
||||
use crate::i2c::{Error, Instance, SclPin, SdaPin};
|
||||
use crate::interrupt::InterruptExt;
|
||||
use crate::pac::i2c;
|
||||
use crate::time::Hertz;
|
||||
use crate::Peripheral;
|
||||
use crate::{interrupt, Peripheral};
|
||||
|
||||
/// Interrupt handler.
|
||||
pub struct InterruptHandler<T: Instance> {
|
||||
_phantom: PhantomData<T>,
|
||||
}
|
||||
|
||||
impl<T: Instance> interrupt::Handler<T::Interrupt> for InterruptHandler<T> {
|
||||
unsafe fn on_interrupt() {
|
||||
let regs = T::regs();
|
||||
let isr = regs.isr().read();
|
||||
|
||||
if isr.tcr() || isr.tc() {
|
||||
T::state().waker.wake();
|
||||
}
|
||||
// The flag can only be cleared by writting to nbytes, we won't do that here, so disable
|
||||
// the interrupt
|
||||
critical_section::with(|_| {
|
||||
regs.cr1().modify(|w| w.set_tcie(false));
|
||||
});
|
||||
}
|
||||
}
|
||||
|
||||
#[non_exhaustive]
|
||||
#[derive(Copy, Clone)]
|
||||
@ -56,13 +78,13 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
|
||||
peri: impl Peripheral<P = T> + 'd,
|
||||
scl: impl Peripheral<P = impl SclPin<T>> + 'd,
|
||||
sda: impl Peripheral<P = impl SdaPin<T>> + 'd,
|
||||
irq: impl Peripheral<P = T::Interrupt> + 'd,
|
||||
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
|
||||
tx_dma: impl Peripheral<P = TXDMA> + 'd,
|
||||
rx_dma: impl Peripheral<P = RXDMA> + 'd,
|
||||
freq: Hertz,
|
||||
config: Config,
|
||||
) -> Self {
|
||||
into_ref!(peri, irq, scl, sda, tx_dma, rx_dma);
|
||||
into_ref!(peri, scl, sda, tx_dma, rx_dma);
|
||||
|
||||
T::enable();
|
||||
T::reset();
|
||||
@ -111,9 +133,8 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
|
||||
});
|
||||
}
|
||||
|
||||
irq.set_handler(Self::on_interrupt);
|
||||
irq.unpend();
|
||||
irq.enable();
|
||||
unsafe { T::Interrupt::steal() }.unpend();
|
||||
unsafe { T::Interrupt::steal() }.enable();
|
||||
|
||||
Self {
|
||||
_peri: peri,
|
||||
@ -122,20 +143,6 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
|
||||
}
|
||||
}
|
||||
|
||||
unsafe fn on_interrupt(_: *mut ()) {
|
||||
let regs = T::regs();
|
||||
let isr = regs.isr().read();
|
||||
|
||||
if isr.tcr() || isr.tc() {
|
||||
T::state().waker.wake();
|
||||
}
|
||||
// The flag can only be cleared by writting to nbytes, we won't do that here, so disable
|
||||
// the interrupt
|
||||
critical_section::with(|_| {
|
||||
regs.cr1().modify(|w| w.set_tcie(false));
|
||||
});
|
||||
}
|
||||
|
||||
fn master_stop(&mut self) {
|
||||
unsafe {
|
||||
T::regs().cr2().write(|w| w.set_stop(true));
|
||||
|
@ -1,4 +0,0 @@
|
||||
pub use critical_section::{CriticalSection, Mutex};
|
||||
pub use embassy_cortex_m::interrupt::*;
|
||||
|
||||
pub use crate::_generated::interrupt::*;
|
@ -6,7 +6,6 @@ pub mod fmt;
|
||||
include!(concat!(env!("OUT_DIR"), "/_macros.rs"));
|
||||
|
||||
// Utilities
|
||||
pub mod interrupt;
|
||||
pub mod time;
|
||||
mod traits;
|
||||
|
||||
@ -73,6 +72,41 @@ pub(crate) mod _generated {
|
||||
include!(concat!(env!("OUT_DIR"), "/_generated.rs"));
|
||||
}
|
||||
|
||||
pub mod interrupt {
|
||||
//! Interrupt definitions and macros to bind them.
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy_cortex_m::interrupt::{Binding, Handler, Interrupt, InterruptExt, Priority};
|
||||
|
||||
pub use crate::_generated::interrupt::*;
|
||||
|
||||
/// Macro to bind interrupts to handlers.
|
||||
///
|
||||
/// This defines the right interrupt handlers, and creates a unit struct (like `struct Irqs;`)
|
||||
/// and implements the right [`Binding`]s for it. You can pass this struct to drivers to
|
||||
/// prove at compile-time that the right interrupts have been bound.
|
||||
// developer note: this macro can't be in `embassy-cortex-m` due to the use of `$crate`.
|
||||
#[macro_export]
|
||||
macro_rules! bind_interrupts {
|
||||
($vis:vis struct $name:ident { $($irq:ident => $($handler:ty),*;)* }) => {
|
||||
$vis struct $name;
|
||||
|
||||
$(
|
||||
#[allow(non_snake_case)]
|
||||
#[no_mangle]
|
||||
unsafe extern "C" fn $irq() {
|
||||
$(
|
||||
<$handler as $crate::interrupt::Handler<$crate::interrupt::$irq>>::on_interrupt();
|
||||
)*
|
||||
}
|
||||
|
||||
$(
|
||||
unsafe impl $crate::interrupt::Binding<$crate::interrupt::$irq, $handler> for $name {}
|
||||
)*
|
||||
)*
|
||||
};
|
||||
}
|
||||
}
|
||||
|
||||
// Reexports
|
||||
pub use _generated::{peripherals, Peripherals};
|
||||
pub use embassy_cortex_m::executor;
|
||||
|
@ -2,6 +2,7 @@
|
||||
|
||||
use core::default::Default;
|
||||
use core::future::poll_fn;
|
||||
use core::marker::PhantomData;
|
||||
use core::ops::{Deref, DerefMut};
|
||||
use core::task::Poll;
|
||||
|
||||
@ -17,7 +18,36 @@ use crate::interrupt::{Interrupt, InterruptExt};
|
||||
use crate::pac::sdmmc::Sdmmc as RegBlock;
|
||||
use crate::rcc::RccPeripheral;
|
||||
use crate::time::Hertz;
|
||||
use crate::{peripherals, Peripheral};
|
||||
use crate::{interrupt, peripherals, Peripheral};
|
||||
|
||||
/// Interrupt handler.
|
||||
pub struct InterruptHandler<T: Instance> {
|
||||
_phantom: PhantomData<T>,
|
||||
}
|
||||
|
||||
impl<T: Instance> InterruptHandler<T> {
|
||||
fn data_interrupts(enable: bool) {
|
||||
let regs = T::regs();
|
||||
// NOTE(unsafe) Atomic write
|
||||
unsafe {
|
||||
regs.maskr().write(|w| {
|
||||
w.set_dcrcfailie(enable);
|
||||
w.set_dtimeoutie(enable);
|
||||
w.set_dataendie(enable);
|
||||
|
||||
#[cfg(sdmmc_v2)]
|
||||
w.set_dabortie(enable);
|
||||
});
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl<T: Instance> interrupt::Handler<T::Interrupt> for InterruptHandler<T> {
|
||||
unsafe fn on_interrupt() {
|
||||
Self::data_interrupts(false);
|
||||
T::state().wake();
|
||||
}
|
||||
}
|
||||
|
||||
/// Frequency used for SD Card initialization. Must be no higher than 400 kHz.
|
||||
const SD_INIT_FREQ: Hertz = Hertz(400_000);
|
||||
@ -223,7 +253,6 @@ impl Default for Config {
|
||||
/// Sdmmc device
|
||||
pub struct Sdmmc<'d, T: Instance, Dma: SdmmcDma<T> = NoDma> {
|
||||
_peri: PeripheralRef<'d, T>,
|
||||
irq: PeripheralRef<'d, T::Interrupt>,
|
||||
#[allow(unused)]
|
||||
dma: PeripheralRef<'d, Dma>,
|
||||
|
||||
@ -247,7 +276,7 @@ pub struct Sdmmc<'d, T: Instance, Dma: SdmmcDma<T> = NoDma> {
|
||||
impl<'d, T: Instance, Dma: SdmmcDma<T>> Sdmmc<'d, T, Dma> {
|
||||
pub fn new_1bit(
|
||||
sdmmc: impl Peripheral<P = T> + 'd,
|
||||
irq: impl Peripheral<P = T::Interrupt> + 'd,
|
||||
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
|
||||
dma: impl Peripheral<P = Dma> + 'd,
|
||||
clk: impl Peripheral<P = impl CkPin<T>> + 'd,
|
||||
cmd: impl Peripheral<P = impl CmdPin<T>> + 'd,
|
||||
@ -268,7 +297,6 @@ impl<'d, T: Instance, Dma: SdmmcDma<T>> Sdmmc<'d, T, Dma> {
|
||||
|
||||
Self::new_inner(
|
||||
sdmmc,
|
||||
irq,
|
||||
dma,
|
||||
clk.map_into(),
|
||||
cmd.map_into(),
|
||||
@ -282,7 +310,7 @@ impl<'d, T: Instance, Dma: SdmmcDma<T>> Sdmmc<'d, T, Dma> {
|
||||
|
||||
pub fn new_4bit(
|
||||
sdmmc: impl Peripheral<P = T> + 'd,
|
||||
irq: impl Peripheral<P = T::Interrupt> + 'd,
|
||||
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
|
||||
dma: impl Peripheral<P = Dma> + 'd,
|
||||
clk: impl Peripheral<P = impl CkPin<T>> + 'd,
|
||||
cmd: impl Peripheral<P = impl CmdPin<T>> + 'd,
|
||||
@ -312,7 +340,6 @@ impl<'d, T: Instance, Dma: SdmmcDma<T>> Sdmmc<'d, T, Dma> {
|
||||
|
||||
Self::new_inner(
|
||||
sdmmc,
|
||||
irq,
|
||||
dma,
|
||||
clk.map_into(),
|
||||
cmd.map_into(),
|
||||
@ -329,7 +356,7 @@ impl<'d, T: Instance, Dma: SdmmcDma<T>> Sdmmc<'d, T, Dma> {
|
||||
impl<'d, T: Instance> Sdmmc<'d, T, NoDma> {
|
||||
pub fn new_1bit(
|
||||
sdmmc: impl Peripheral<P = T> + 'd,
|
||||
irq: impl Peripheral<P = T::Interrupt> + 'd,
|
||||
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
|
||||
clk: impl Peripheral<P = impl CkPin<T>> + 'd,
|
||||
cmd: impl Peripheral<P = impl CmdPin<T>> + 'd,
|
||||
d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
|
||||
@ -349,7 +376,6 @@ impl<'d, T: Instance> Sdmmc<'d, T, NoDma> {
|
||||
|
||||
Self::new_inner(
|
||||
sdmmc,
|
||||
irq,
|
||||
NoDma.into_ref(),
|
||||
clk.map_into(),
|
||||
cmd.map_into(),
|
||||
@ -363,7 +389,7 @@ impl<'d, T: Instance> Sdmmc<'d, T, NoDma> {
|
||||
|
||||
pub fn new_4bit(
|
||||
sdmmc: impl Peripheral<P = T> + 'd,
|
||||
irq: impl Peripheral<P = T::Interrupt> + 'd,
|
||||
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
|
||||
clk: impl Peripheral<P = impl CkPin<T>> + 'd,
|
||||
cmd: impl Peripheral<P = impl CmdPin<T>> + 'd,
|
||||
d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
|
||||
@ -392,7 +418,6 @@ impl<'d, T: Instance> Sdmmc<'d, T, NoDma> {
|
||||
|
||||
Self::new_inner(
|
||||
sdmmc,
|
||||
irq,
|
||||
NoDma.into_ref(),
|
||||
clk.map_into(),
|
||||
cmd.map_into(),
|
||||
@ -408,7 +433,6 @@ impl<'d, T: Instance> Sdmmc<'d, T, NoDma> {
|
||||
impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
|
||||
fn new_inner(
|
||||
sdmmc: impl Peripheral<P = T> + 'd,
|
||||
irq: impl Peripheral<P = T::Interrupt> + 'd,
|
||||
dma: impl Peripheral<P = Dma> + 'd,
|
||||
clk: PeripheralRef<'d, AnyPin>,
|
||||
cmd: PeripheralRef<'d, AnyPin>,
|
||||
@ -418,14 +442,13 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
|
||||
d3: Option<PeripheralRef<'d, AnyPin>>,
|
||||
config: Config,
|
||||
) -> Self {
|
||||
into_ref!(sdmmc, irq, dma);
|
||||
into_ref!(sdmmc, dma);
|
||||
|
||||
T::enable();
|
||||
T::reset();
|
||||
|
||||
irq.set_handler(Self::on_interrupt);
|
||||
irq.unpend();
|
||||
irq.enable();
|
||||
unsafe { T::Interrupt::steal() }.unpend();
|
||||
unsafe { T::Interrupt::steal() }.enable();
|
||||
|
||||
let regs = T::regs();
|
||||
unsafe {
|
||||
@ -451,7 +474,6 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
|
||||
|
||||
Self {
|
||||
_peri: sdmmc,
|
||||
irq,
|
||||
dma,
|
||||
|
||||
clk,
|
||||
@ -691,7 +713,7 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
|
||||
let on_drop = OnDrop::new(|| unsafe { Self::on_drop() });
|
||||
|
||||
let transfer = self.prepare_datapath_read(&mut status, 64, 6);
|
||||
Self::data_interrupts(true);
|
||||
InterruptHandler::<T>::data_interrupts(true);
|
||||
Self::cmd(Cmd::cmd6(set_function), true)?; // CMD6
|
||||
|
||||
let res = poll_fn(|cx| {
|
||||
@ -767,7 +789,7 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
|
||||
let on_drop = OnDrop::new(|| unsafe { Self::on_drop() });
|
||||
|
||||
let transfer = self.prepare_datapath_read(&mut status, 64, 6);
|
||||
Self::data_interrupts(true);
|
||||
InterruptHandler::<T>::data_interrupts(true);
|
||||
Self::cmd(Cmd::card_status(0), true)?;
|
||||
|
||||
let res = poll_fn(|cx| {
|
||||
@ -849,23 +871,6 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
|
||||
}
|
||||
}
|
||||
|
||||
/// Enables the interrupts for data transfer
|
||||
#[inline(always)]
|
||||
fn data_interrupts(enable: bool) {
|
||||
let regs = T::regs();
|
||||
// NOTE(unsafe) Atomic write
|
||||
unsafe {
|
||||
regs.maskr().write(|w| {
|
||||
w.set_dcrcfailie(enable);
|
||||
w.set_dtimeoutie(enable);
|
||||
w.set_dataendie(enable);
|
||||
|
||||
#[cfg(sdmmc_v2)]
|
||||
w.set_dabortie(enable);
|
||||
});
|
||||
}
|
||||
}
|
||||
|
||||
async fn get_scr(&mut self, card: &mut Card) -> Result<(), Error> {
|
||||
// Read the the 64-bit SCR register
|
||||
Self::cmd(Cmd::set_block_length(8), false)?; // CMD16
|
||||
@ -878,7 +883,7 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
|
||||
let on_drop = OnDrop::new(|| unsafe { Self::on_drop() });
|
||||
|
||||
let transfer = self.prepare_datapath_read(&mut scr[..], 8, 3);
|
||||
Self::data_interrupts(true);
|
||||
InterruptHandler::<T>::data_interrupts(true);
|
||||
Self::cmd(Cmd::cmd51(), true)?;
|
||||
|
||||
let res = poll_fn(|cx| {
|
||||
@ -996,7 +1001,7 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
|
||||
// Wait for the abort
|
||||
while Self::data_active() {}
|
||||
}
|
||||
Self::data_interrupts(false);
|
||||
InterruptHandler::<T>::data_interrupts(false);
|
||||
Self::clear_interrupt_flags();
|
||||
Self::stop_datapath();
|
||||
}
|
||||
@ -1170,7 +1175,7 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
|
||||
let on_drop = OnDrop::new(|| unsafe { Self::on_drop() });
|
||||
|
||||
let transfer = self.prepare_datapath_read(buffer, 512, 9);
|
||||
Self::data_interrupts(true);
|
||||
InterruptHandler::<T>::data_interrupts(true);
|
||||
Self::cmd(Cmd::read_single_block(address), true)?;
|
||||
|
||||
let res = poll_fn(|cx| {
|
||||
@ -1219,7 +1224,7 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
|
||||
Self::cmd(Cmd::write_single_block(address), true)?;
|
||||
|
||||
let transfer = self.prepare_datapath_write(buffer, 512, 9);
|
||||
Self::data_interrupts(true);
|
||||
InterruptHandler::<T>::data_interrupts(true);
|
||||
|
||||
#[cfg(sdmmc_v2)]
|
||||
Self::cmd(Cmd::write_single_block(address), true)?;
|
||||
@ -1279,17 +1284,11 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
|
||||
pub fn clock(&self) -> Hertz {
|
||||
self.clock
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
fn on_interrupt(_: *mut ()) {
|
||||
Self::data_interrupts(false);
|
||||
T::state().wake();
|
||||
}
|
||||
}
|
||||
|
||||
impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Drop for Sdmmc<'d, T, Dma> {
|
||||
fn drop(&mut self) {
|
||||
self.irq.disable();
|
||||
unsafe { T::Interrupt::steal() }.disable();
|
||||
unsafe { Self::on_drop() };
|
||||
|
||||
critical_section::with(|_| unsafe {
|
||||
|
@ -4,13 +4,14 @@ use core::sync::atomic::{compiler_fence, Ordering};
|
||||
use core::{mem, ptr};
|
||||
|
||||
use atomic_polyfill::{AtomicU32, AtomicU8};
|
||||
use critical_section::CriticalSection;
|
||||
use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
|
||||
use embassy_sync::blocking_mutex::Mutex;
|
||||
use embassy_time::driver::{AlarmHandle, Driver};
|
||||
use embassy_time::TICK_HZ;
|
||||
use stm32_metapac::timer::regs;
|
||||
|
||||
use crate::interrupt::{CriticalSection, InterruptExt};
|
||||
use crate::interrupt::InterruptExt;
|
||||
use crate::pac::timer::vals;
|
||||
use crate::rcc::sealed::RccPeripheral;
|
||||
use crate::timer::sealed::{Basic16bitInstance as BasicInstance, GeneralPurpose16bitInstance as Instance};
|
||||
|
@ -1,7 +1,6 @@
|
||||
use core::mem::MaybeUninit;
|
||||
|
||||
use bit_field::BitField;
|
||||
use embassy_cortex_m::interrupt::InterruptExt;
|
||||
use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
|
||||
use embassy_sync::channel::Channel;
|
||||
|
||||
@ -12,7 +11,7 @@ use self::mm::MemoryManager;
|
||||
use self::shci::{shci_ble_init, ShciBleInitCmdParam};
|
||||
use self::sys::Sys;
|
||||
use self::unsafe_linked_list::LinkedListNode;
|
||||
use crate::_generated::interrupt::{IPCC_C1_RX, IPCC_C1_TX};
|
||||
use crate::interrupt;
|
||||
use crate::ipcc::Ipcc;
|
||||
|
||||
mod ble;
|
||||
@ -55,6 +54,19 @@ pub struct FusInfoTable {
|
||||
fus_info: u32,
|
||||
}
|
||||
|
||||
/// Interrupt handler.
|
||||
pub struct ReceiveInterruptHandler {}
|
||||
|
||||
impl interrupt::Handler<interrupt::IPCC_C1_RX> for ReceiveInterruptHandler {
|
||||
unsafe fn on_interrupt() {}
|
||||
}
|
||||
|
||||
pub struct TransmitInterruptHandler {}
|
||||
|
||||
impl interrupt::Handler<interrupt::IPCC_C1_TX> for TransmitInterruptHandler {
|
||||
unsafe fn on_interrupt() {}
|
||||
}
|
||||
|
||||
/// # Version
|
||||
/// - 0 -> 3 = Build - 0: Untracked - 15:Released - x: Tracked version
|
||||
/// - 4 -> 7 = branch - 0: Mass Market - x: ...
|
||||
@ -285,7 +297,11 @@ pub struct TlMbox {
|
||||
|
||||
impl TlMbox {
|
||||
/// initializes low-level transport between CPU1 and BLE stack on CPU2
|
||||
pub fn init(ipcc: &mut Ipcc, rx_irq: IPCC_C1_RX, tx_irq: IPCC_C1_TX) -> TlMbox {
|
||||
pub fn init(
|
||||
ipcc: &mut Ipcc,
|
||||
_irqs: impl interrupt::Binding<interrupt::IPCC_C1_RX, ReceiveInterruptHandler>
|
||||
+ interrupt::Binding<interrupt::IPCC_C1_TX, TransmitInterruptHandler>,
|
||||
) -> TlMbox {
|
||||
unsafe {
|
||||
TL_REF_TABLE = MaybeUninit::new(RefTable {
|
||||
device_info_table: TL_DEVICE_INFO_TABLE.as_ptr(),
|
||||
@ -326,23 +342,23 @@ impl TlMbox {
|
||||
let _ble = Ble::new(ipcc);
|
||||
let _mm = MemoryManager::new();
|
||||
|
||||
rx_irq.disable();
|
||||
tx_irq.disable();
|
||||
|
||||
rx_irq.set_handler_context(ipcc.as_mut_ptr() as *mut ());
|
||||
tx_irq.set_handler_context(ipcc.as_mut_ptr() as *mut ());
|
||||
|
||||
rx_irq.set_handler(|ipcc| {
|
||||
let ipcc: &mut Ipcc = unsafe { &mut *ipcc.cast() };
|
||||
Self::interrupt_ipcc_rx_handler(ipcc);
|
||||
});
|
||||
tx_irq.set_handler(|ipcc| {
|
||||
let ipcc: &mut Ipcc = unsafe { &mut *ipcc.cast() };
|
||||
Self::interrupt_ipcc_tx_handler(ipcc);
|
||||
});
|
||||
|
||||
rx_irq.enable();
|
||||
tx_irq.enable();
|
||||
// rx_irq.disable();
|
||||
// tx_irq.disable();
|
||||
//
|
||||
// rx_irq.set_handler_context(ipcc.as_mut_ptr() as *mut ());
|
||||
// tx_irq.set_handler_context(ipcc.as_mut_ptr() as *mut ());
|
||||
//
|
||||
// rx_irq.set_handler(|ipcc| {
|
||||
// let ipcc: &mut Ipcc = unsafe { &mut *ipcc.cast() };
|
||||
// Self::interrupt_ipcc_rx_handler(ipcc);
|
||||
// });
|
||||
// tx_irq.set_handler(|ipcc| {
|
||||
// let ipcc: &mut Ipcc = unsafe { &mut *ipcc.cast() };
|
||||
// Self::interrupt_ipcc_tx_handler(ipcc);
|
||||
// });
|
||||
//
|
||||
// rx_irq.enable();
|
||||
// tx_irq.enable();
|
||||
|
||||
TlMbox { _sys, _ble, _mm }
|
||||
}
|
||||
@ -374,6 +390,7 @@ impl TlMbox {
|
||||
TL_CHANNEL.recv().await
|
||||
}
|
||||
|
||||
#[allow(dead_code)]
|
||||
fn interrupt_ipcc_rx_handler(ipcc: &mut Ipcc) {
|
||||
if ipcc.is_rx_pending(channels::cpu2::IPCC_SYSTEM_EVENT_CHANNEL) {
|
||||
sys::Sys::evt_handler(ipcc);
|
||||
@ -384,6 +401,7 @@ impl TlMbox {
|
||||
}
|
||||
}
|
||||
|
||||
#[allow(dead_code)]
|
||||
fn interrupt_ipcc_tx_handler(ipcc: &mut Ipcc) {
|
||||
if ipcc.is_tx_pending(channels::cpu1::IPCC_SYSTEM_CMD_RSP_CHANNEL) {
|
||||
// TODO: handle this case
|
||||
|
@ -8,6 +8,78 @@ use embassy_sync::waitqueue::AtomicWaker;
|
||||
|
||||
use super::*;
|
||||
|
||||
/// Interrupt handler.
|
||||
pub struct InterruptHandler<T: BasicInstance> {
|
||||
_phantom: PhantomData<T>,
|
||||
}
|
||||
|
||||
impl<T: BasicInstance> interrupt::Handler<T::Interrupt> for InterruptHandler<T> {
|
||||
unsafe fn on_interrupt() {
|
||||
let r = T::regs();
|
||||
let state = T::buffered_state();
|
||||
|
||||
// RX
|
||||
unsafe {
|
||||
let sr = sr(r).read();
|
||||
clear_interrupt_flags(r, sr);
|
||||
|
||||
if sr.rxne() {
|
||||
if sr.pe() {
|
||||
warn!("Parity error");
|
||||
}
|
||||
if sr.fe() {
|
||||
warn!("Framing error");
|
||||
}
|
||||
if sr.ne() {
|
||||
warn!("Noise error");
|
||||
}
|
||||
if sr.ore() {
|
||||
warn!("Overrun error");
|
||||
}
|
||||
|
||||
let mut rx_writer = state.rx_buf.writer();
|
||||
let buf = rx_writer.push_slice();
|
||||
if !buf.is_empty() {
|
||||
// This read also clears the error and idle interrupt flags on v1.
|
||||
buf[0] = rdr(r).read_volatile();
|
||||
rx_writer.push_done(1);
|
||||
} else {
|
||||
// FIXME: Should we disable any further RX interrupts when the buffer becomes full.
|
||||
}
|
||||
|
||||
if state.rx_buf.is_full() {
|
||||
state.rx_waker.wake();
|
||||
}
|
||||
}
|
||||
|
||||
if sr.idle() {
|
||||
state.rx_waker.wake();
|
||||
};
|
||||
}
|
||||
|
||||
// TX
|
||||
unsafe {
|
||||
if sr(r).read().txe() {
|
||||
let mut tx_reader = state.tx_buf.reader();
|
||||
let buf = tx_reader.pop_slice();
|
||||
if !buf.is_empty() {
|
||||
r.cr1().modify(|w| {
|
||||
w.set_txeie(true);
|
||||
});
|
||||
tdr(r).write_volatile(buf[0].into());
|
||||
tx_reader.pop_done(1);
|
||||
state.tx_waker.wake();
|
||||
} else {
|
||||
// Disable interrupt until we have something to transmit again
|
||||
r.cr1().modify(|w| {
|
||||
w.set_txeie(false);
|
||||
});
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pub struct State {
|
||||
rx_waker: AtomicWaker,
|
||||
rx_buf: RingBuffer,
|
||||
@ -43,7 +115,7 @@ pub struct BufferedUartRx<'d, T: BasicInstance> {
|
||||
impl<'d, T: BasicInstance> BufferedUart<'d, T> {
|
||||
pub fn new(
|
||||
peri: impl Peripheral<P = T> + 'd,
|
||||
irq: impl Peripheral<P = T::Interrupt> + 'd,
|
||||
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
|
||||
rx: impl Peripheral<P = impl RxPin<T>> + 'd,
|
||||
tx: impl Peripheral<P = impl TxPin<T>> + 'd,
|
||||
tx_buffer: &'d mut [u8],
|
||||
@ -53,12 +125,12 @@ impl<'d, T: BasicInstance> BufferedUart<'d, T> {
|
||||
T::enable();
|
||||
T::reset();
|
||||
|
||||
Self::new_inner(peri, irq, rx, tx, tx_buffer, rx_buffer, config)
|
||||
Self::new_inner(peri, rx, tx, tx_buffer, rx_buffer, config)
|
||||
}
|
||||
|
||||
pub fn new_with_rtscts(
|
||||
peri: impl Peripheral<P = T> + 'd,
|
||||
irq: impl Peripheral<P = T::Interrupt> + 'd,
|
||||
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
|
||||
rx: impl Peripheral<P = impl RxPin<T>> + 'd,
|
||||
tx: impl Peripheral<P = impl TxPin<T>> + 'd,
|
||||
rts: impl Peripheral<P = impl RtsPin<T>> + 'd,
|
||||
@ -81,13 +153,13 @@ impl<'d, T: BasicInstance> BufferedUart<'d, T> {
|
||||
});
|
||||
}
|
||||
|
||||
Self::new_inner(peri, irq, rx, tx, tx_buffer, rx_buffer, config)
|
||||
Self::new_inner(peri, rx, tx, tx_buffer, rx_buffer, config)
|
||||
}
|
||||
|
||||
#[cfg(not(any(usart_v1, usart_v2)))]
|
||||
pub fn new_with_de(
|
||||
peri: impl Peripheral<P = T> + 'd,
|
||||
irq: impl Peripheral<P = T::Interrupt> + 'd,
|
||||
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
|
||||
rx: impl Peripheral<P = impl RxPin<T>> + 'd,
|
||||
tx: impl Peripheral<P = impl TxPin<T>> + 'd,
|
||||
de: impl Peripheral<P = impl DePin<T>> + 'd,
|
||||
@ -107,19 +179,18 @@ impl<'d, T: BasicInstance> BufferedUart<'d, T> {
|
||||
});
|
||||
}
|
||||
|
||||
Self::new_inner(peri, irq, rx, tx, tx_buffer, rx_buffer, config)
|
||||
Self::new_inner(peri, rx, tx, tx_buffer, rx_buffer, config)
|
||||
}
|
||||
|
||||
fn new_inner(
|
||||
_peri: impl Peripheral<P = T> + 'd,
|
||||
irq: impl Peripheral<P = T::Interrupt> + 'd,
|
||||
rx: impl Peripheral<P = impl RxPin<T>> + 'd,
|
||||
tx: impl Peripheral<P = impl TxPin<T>> + 'd,
|
||||
tx_buffer: &'d mut [u8],
|
||||
rx_buffer: &'d mut [u8],
|
||||
config: Config,
|
||||
) -> BufferedUart<'d, T> {
|
||||
into_ref!(_peri, rx, tx, irq);
|
||||
into_ref!(_peri, rx, tx);
|
||||
|
||||
let state = T::buffered_state();
|
||||
let len = tx_buffer.len();
|
||||
@ -145,9 +216,8 @@ impl<'d, T: BasicInstance> BufferedUart<'d, T> {
|
||||
});
|
||||
}
|
||||
|
||||
irq.set_handler(on_interrupt::<T>);
|
||||
irq.unpend();
|
||||
irq.enable();
|
||||
unsafe { T::Interrupt::steal() }.unpend();
|
||||
unsafe { T::Interrupt::steal() }.enable();
|
||||
|
||||
Self {
|
||||
rx: BufferedUartRx { phantom: PhantomData },
|
||||
@ -336,71 +406,6 @@ impl<'d, T: BasicInstance> Drop for BufferedUartTx<'d, T> {
|
||||
}
|
||||
}
|
||||
|
||||
unsafe fn on_interrupt<T: BasicInstance>(_: *mut ()) {
|
||||
let r = T::regs();
|
||||
let state = T::buffered_state();
|
||||
|
||||
// RX
|
||||
unsafe {
|
||||
let sr = sr(r).read();
|
||||
clear_interrupt_flags(r, sr);
|
||||
|
||||
if sr.rxne() {
|
||||
if sr.pe() {
|
||||
warn!("Parity error");
|
||||
}
|
||||
if sr.fe() {
|
||||
warn!("Framing error");
|
||||
}
|
||||
if sr.ne() {
|
||||
warn!("Noise error");
|
||||
}
|
||||
if sr.ore() {
|
||||
warn!("Overrun error");
|
||||
}
|
||||
|
||||
let mut rx_writer = state.rx_buf.writer();
|
||||
let buf = rx_writer.push_slice();
|
||||
if !buf.is_empty() {
|
||||
// This read also clears the error and idle interrupt flags on v1.
|
||||
buf[0] = rdr(r).read_volatile();
|
||||
rx_writer.push_done(1);
|
||||
} else {
|
||||
// FIXME: Should we disable any further RX interrupts when the buffer becomes full.
|
||||
}
|
||||
|
||||
if state.rx_buf.is_full() {
|
||||
state.rx_waker.wake();
|
||||
}
|
||||
}
|
||||
|
||||
if sr.idle() {
|
||||
state.rx_waker.wake();
|
||||
};
|
||||
}
|
||||
|
||||
// TX
|
||||
unsafe {
|
||||
if sr(r).read().txe() {
|
||||
let mut tx_reader = state.tx_buf.reader();
|
||||
let buf = tx_reader.pop_slice();
|
||||
if !buf.is_empty() {
|
||||
r.cr1().modify(|w| {
|
||||
w.set_txeie(true);
|
||||
});
|
||||
tdr(r).write_volatile(buf[0].into());
|
||||
tx_reader.pop_done(1);
|
||||
state.tx_waker.wake();
|
||||
} else {
|
||||
// Disable interrupt until we have something to transmit again
|
||||
r.cr1().modify(|w| {
|
||||
w.set_txeie(false);
|
||||
});
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl embedded_io::Error for Error {
|
||||
fn kind(&self) -> embedded_io::ErrorKind {
|
||||
embedded_io::ErrorKind::Other
|
||||
|
@ -5,7 +5,7 @@ use core::marker::PhantomData;
|
||||
use core::sync::atomic::{compiler_fence, Ordering};
|
||||
use core::task::Poll;
|
||||
|
||||
use embassy_cortex_m::interrupt::InterruptExt;
|
||||
use embassy_cortex_m::interrupt::{Interrupt, InterruptExt};
|
||||
use embassy_hal_common::drop::OnDrop;
|
||||
use embassy_hal_common::{into_ref, PeripheralRef};
|
||||
use futures::future::{select, Either};
|
||||
@ -18,7 +18,71 @@ use crate::pac::usart::Lpuart as Regs;
|
||||
use crate::pac::usart::Usart as Regs;
|
||||
use crate::pac::usart::{regs, vals};
|
||||
use crate::time::Hertz;
|
||||
use crate::{peripherals, Peripheral};
|
||||
use crate::{interrupt, peripherals, Peripheral};
|
||||
|
||||
/// Interrupt handler.
|
||||
pub struct InterruptHandler<T: BasicInstance> {
|
||||
_phantom: PhantomData<T>,
|
||||
}
|
||||
|
||||
impl<T: BasicInstance> interrupt::Handler<T::Interrupt> for InterruptHandler<T> {
|
||||
unsafe fn on_interrupt() {
|
||||
let r = T::regs();
|
||||
let s = T::state();
|
||||
|
||||
let (sr, cr1, cr3) = unsafe { (sr(r).read(), r.cr1().read(), r.cr3().read()) };
|
||||
|
||||
let mut wake = false;
|
||||
let has_errors = (sr.pe() && cr1.peie()) || ((sr.fe() || sr.ne() || sr.ore()) && cr3.eie());
|
||||
if has_errors {
|
||||
// clear all interrupts and DMA Rx Request
|
||||
unsafe {
|
||||
r.cr1().modify(|w| {
|
||||
// disable RXNE interrupt
|
||||
w.set_rxneie(false);
|
||||
// disable parity interrupt
|
||||
w.set_peie(false);
|
||||
// disable idle line interrupt
|
||||
w.set_idleie(false);
|
||||
});
|
||||
r.cr3().modify(|w| {
|
||||
// disable Error Interrupt: (Frame error, Noise error, Overrun error)
|
||||
w.set_eie(false);
|
||||
// disable DMA Rx Request
|
||||
w.set_dmar(false);
|
||||
});
|
||||
}
|
||||
|
||||
wake = true;
|
||||
} else {
|
||||
if cr1.idleie() && sr.idle() {
|
||||
// IDLE detected: no more data will come
|
||||
unsafe {
|
||||
r.cr1().modify(|w| {
|
||||
// disable idle line detection
|
||||
w.set_idleie(false);
|
||||
});
|
||||
}
|
||||
|
||||
wake = true;
|
||||
}
|
||||
|
||||
if cr1.rxneie() {
|
||||
// We cannot check the RXNE flag as it is auto-cleared by the DMA controller
|
||||
|
||||
// It is up to the listener to determine if this in fact was a RX event and disable the RXNE detection
|
||||
|
||||
wake = true;
|
||||
}
|
||||
}
|
||||
|
||||
if wake {
|
||||
compiler_fence(Ordering::SeqCst);
|
||||
|
||||
s.rx_waker.wake();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#[derive(Clone, Copy, PartialEq, Eq, Debug)]
|
||||
pub enum DataBits {
|
||||
@ -215,7 +279,7 @@ impl<'d, T: BasicInstance, RxDma> UartRx<'d, T, RxDma> {
|
||||
/// Useful if you only want Uart Rx. It saves 1 pin and consumes a little less power.
|
||||
pub fn new(
|
||||
peri: impl Peripheral<P = T> + 'd,
|
||||
irq: impl Peripheral<P = T::Interrupt> + 'd,
|
||||
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
|
||||
rx: impl Peripheral<P = impl RxPin<T>> + 'd,
|
||||
rx_dma: impl Peripheral<P = RxDma> + 'd,
|
||||
config: Config,
|
||||
@ -223,12 +287,12 @@ impl<'d, T: BasicInstance, RxDma> UartRx<'d, T, RxDma> {
|
||||
T::enable();
|
||||
T::reset();
|
||||
|
||||
Self::new_inner(peri, irq, rx, rx_dma, config)
|
||||
Self::new_inner(peri, rx, rx_dma, config)
|
||||
}
|
||||
|
||||
pub fn new_with_rts(
|
||||
peri: impl Peripheral<P = T> + 'd,
|
||||
irq: impl Peripheral<P = T::Interrupt> + 'd,
|
||||
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
|
||||
rx: impl Peripheral<P = impl RxPin<T>> + 'd,
|
||||
rts: impl Peripheral<P = impl RtsPin<T>> + 'd,
|
||||
rx_dma: impl Peripheral<P = RxDma> + 'd,
|
||||
@ -246,17 +310,16 @@ impl<'d, T: BasicInstance, RxDma> UartRx<'d, T, RxDma> {
|
||||
});
|
||||
}
|
||||
|
||||
Self::new_inner(peri, irq, rx, rx_dma, config)
|
||||
Self::new_inner(peri, rx, rx_dma, config)
|
||||
}
|
||||
|
||||
fn new_inner(
|
||||
peri: impl Peripheral<P = T> + 'd,
|
||||
irq: impl Peripheral<P = T::Interrupt> + 'd,
|
||||
rx: impl Peripheral<P = impl RxPin<T>> + 'd,
|
||||
rx_dma: impl Peripheral<P = RxDma> + 'd,
|
||||
config: Config,
|
||||
) -> Self {
|
||||
into_ref!(peri, irq, rx, rx_dma);
|
||||
into_ref!(peri, rx, rx_dma);
|
||||
|
||||
let r = T::regs();
|
||||
|
||||
@ -266,9 +329,8 @@ impl<'d, T: BasicInstance, RxDma> UartRx<'d, T, RxDma> {
|
||||
|
||||
configure(r, &config, T::frequency(), T::KIND, true, false);
|
||||
|
||||
irq.set_handler(Self::on_interrupt);
|
||||
irq.unpend();
|
||||
irq.enable();
|
||||
unsafe { T::Interrupt::steal() }.unpend();
|
||||
unsafe { T::Interrupt::steal() }.enable();
|
||||
|
||||
// create state once!
|
||||
let _s = T::state();
|
||||
@ -282,63 +344,6 @@ impl<'d, T: BasicInstance, RxDma> UartRx<'d, T, RxDma> {
|
||||
}
|
||||
}
|
||||
|
||||
fn on_interrupt(_: *mut ()) {
|
||||
let r = T::regs();
|
||||
let s = T::state();
|
||||
|
||||
let (sr, cr1, cr3) = unsafe { (sr(r).read(), r.cr1().read(), r.cr3().read()) };
|
||||
|
||||
let mut wake = false;
|
||||
let has_errors = (sr.pe() && cr1.peie()) || ((sr.fe() || sr.ne() || sr.ore()) && cr3.eie());
|
||||
if has_errors {
|
||||
// clear all interrupts and DMA Rx Request
|
||||
unsafe {
|
||||
r.cr1().modify(|w| {
|
||||
// disable RXNE interrupt
|
||||
w.set_rxneie(false);
|
||||
// disable parity interrupt
|
||||
w.set_peie(false);
|
||||
// disable idle line interrupt
|
||||
w.set_idleie(false);
|
||||
});
|
||||
r.cr3().modify(|w| {
|
||||
// disable Error Interrupt: (Frame error, Noise error, Overrun error)
|
||||
w.set_eie(false);
|
||||
// disable DMA Rx Request
|
||||
w.set_dmar(false);
|
||||
});
|
||||
}
|
||||
|
||||
wake = true;
|
||||
} else {
|
||||
if cr1.idleie() && sr.idle() {
|
||||
// IDLE detected: no more data will come
|
||||
unsafe {
|
||||
r.cr1().modify(|w| {
|
||||
// disable idle line detection
|
||||
w.set_idleie(false);
|
||||
});
|
||||
}
|
||||
|
||||
wake = true;
|
||||
}
|
||||
|
||||
if cr1.rxneie() {
|
||||
// We cannot check the RXNE flag as it is auto-cleared by the DMA controller
|
||||
|
||||
// It is up to the listener to determine if this in fact was a RX event and disable the RXNE detection
|
||||
|
||||
wake = true;
|
||||
}
|
||||
}
|
||||
|
||||
if wake {
|
||||
compiler_fence(Ordering::SeqCst);
|
||||
|
||||
s.rx_waker.wake();
|
||||
}
|
||||
}
|
||||
|
||||
#[cfg(any(usart_v1, usart_v2))]
|
||||
unsafe fn check_rx_flags(&mut self) -> Result<bool, Error> {
|
||||
let r = T::regs();
|
||||
@ -643,7 +648,7 @@ impl<'d, T: BasicInstance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
|
||||
peri: impl Peripheral<P = T> + 'd,
|
||||
rx: impl Peripheral<P = impl RxPin<T>> + 'd,
|
||||
tx: impl Peripheral<P = impl TxPin<T>> + 'd,
|
||||
irq: impl Peripheral<P = T::Interrupt> + 'd,
|
||||
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
|
||||
tx_dma: impl Peripheral<P = TxDma> + 'd,
|
||||
rx_dma: impl Peripheral<P = RxDma> + 'd,
|
||||
config: Config,
|
||||
@ -651,14 +656,14 @@ impl<'d, T: BasicInstance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
|
||||
T::enable();
|
||||
T::reset();
|
||||
|
||||
Self::new_inner(peri, rx, tx, irq, tx_dma, rx_dma, config)
|
||||
Self::new_inner(peri, rx, tx, tx_dma, rx_dma, config)
|
||||
}
|
||||
|
||||
pub fn new_with_rtscts(
|
||||
peri: impl Peripheral<P = T> + 'd,
|
||||
rx: impl Peripheral<P = impl RxPin<T>> + 'd,
|
||||
tx: impl Peripheral<P = impl TxPin<T>> + 'd,
|
||||
irq: impl Peripheral<P = T::Interrupt> + 'd,
|
||||
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
|
||||
rts: impl Peripheral<P = impl RtsPin<T>> + 'd,
|
||||
cts: impl Peripheral<P = impl CtsPin<T>> + 'd,
|
||||
tx_dma: impl Peripheral<P = TxDma> + 'd,
|
||||
@ -678,7 +683,7 @@ impl<'d, T: BasicInstance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
|
||||
w.set_ctse(true);
|
||||
});
|
||||
}
|
||||
Self::new_inner(peri, rx, tx, irq, tx_dma, rx_dma, config)
|
||||
Self::new_inner(peri, rx, tx, tx_dma, rx_dma, config)
|
||||
}
|
||||
|
||||
#[cfg(not(any(usart_v1, usart_v2)))]
|
||||
@ -686,7 +691,7 @@ impl<'d, T: BasicInstance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
|
||||
peri: impl Peripheral<P = T> + 'd,
|
||||
rx: impl Peripheral<P = impl RxPin<T>> + 'd,
|
||||
tx: impl Peripheral<P = impl TxPin<T>> + 'd,
|
||||
irq: impl Peripheral<P = T::Interrupt> + 'd,
|
||||
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
|
||||
de: impl Peripheral<P = impl DePin<T>> + 'd,
|
||||
tx_dma: impl Peripheral<P = TxDma> + 'd,
|
||||
rx_dma: impl Peripheral<P = RxDma> + 'd,
|
||||
@ -703,19 +708,18 @@ impl<'d, T: BasicInstance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
|
||||
w.set_dem(true);
|
||||
});
|
||||
}
|
||||
Self::new_inner(peri, rx, tx, irq, tx_dma, rx_dma, config)
|
||||
Self::new_inner(peri, rx, tx, tx_dma, rx_dma, config)
|
||||
}
|
||||
|
||||
fn new_inner(
|
||||
peri: impl Peripheral<P = T> + 'd,
|
||||
rx: impl Peripheral<P = impl RxPin<T>> + 'd,
|
||||
tx: impl Peripheral<P = impl TxPin<T>> + 'd,
|
||||
irq: impl Peripheral<P = T::Interrupt> + 'd,
|
||||
tx_dma: impl Peripheral<P = TxDma> + 'd,
|
||||
rx_dma: impl Peripheral<P = RxDma> + 'd,
|
||||
config: Config,
|
||||
) -> Self {
|
||||
into_ref!(peri, rx, tx, irq, tx_dma, rx_dma);
|
||||
into_ref!(peri, rx, tx, tx_dma, rx_dma);
|
||||
|
||||
let r = T::regs();
|
||||
|
||||
@ -726,9 +730,8 @@ impl<'d, T: BasicInstance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
|
||||
|
||||
configure(r, &config, T::frequency(), T::KIND, true, true);
|
||||
|
||||
irq.set_handler(UartRx::<T, RxDma>::on_interrupt);
|
||||
irq.unpend();
|
||||
irq.enable();
|
||||
unsafe { T::Interrupt::steal() }.unpend();
|
||||
unsafe { T::Interrupt::steal() }.enable();
|
||||
|
||||
// create state once!
|
||||
let _s = T::state();
|
||||
@ -1068,6 +1071,9 @@ mod eio {
|
||||
|
||||
#[cfg(feature = "nightly")]
|
||||
pub use buffered::*;
|
||||
|
||||
#[cfg(feature = "nightly")]
|
||||
pub use crate::usart::buffered::InterruptHandler as BufferedInterruptHandler;
|
||||
#[cfg(feature = "nightly")]
|
||||
mod buffered;
|
||||
|
||||
|
@ -14,12 +14,99 @@ use embassy_usb_driver::{
|
||||
|
||||
use super::{DmPin, DpPin, Instance};
|
||||
use crate::gpio::sealed::AFType;
|
||||
use crate::interrupt::InterruptExt;
|
||||
use crate::interrupt::{Interrupt, InterruptExt};
|
||||
use crate::pac::usb::regs;
|
||||
use crate::pac::usb::vals::{EpType, Stat};
|
||||
use crate::pac::USBRAM;
|
||||
use crate::rcc::sealed::RccPeripheral;
|
||||
use crate::Peripheral;
|
||||
use crate::{interrupt, Peripheral};
|
||||
|
||||
/// Interrupt handler.
|
||||
pub struct InterruptHandler<T: Instance> {
|
||||
_phantom: PhantomData<T>,
|
||||
}
|
||||
|
||||
impl<T: Instance> interrupt::Handler<T::Interrupt> for InterruptHandler<T> {
|
||||
unsafe fn on_interrupt() {
|
||||
unsafe {
|
||||
let regs = T::regs();
|
||||
//let x = regs.istr().read().0;
|
||||
//trace!("USB IRQ: {:08x}", x);
|
||||
|
||||
let istr = regs.istr().read();
|
||||
|
||||
if istr.susp() {
|
||||
//trace!("USB IRQ: susp");
|
||||
IRQ_SUSPEND.store(true, Ordering::Relaxed);
|
||||
regs.cntr().modify(|w| {
|
||||
w.set_fsusp(true);
|
||||
w.set_lpmode(true);
|
||||
});
|
||||
|
||||
// Write 0 to clear.
|
||||
let mut clear = regs::Istr(!0);
|
||||
clear.set_susp(false);
|
||||
regs.istr().write_value(clear);
|
||||
|
||||
// Wake main thread.
|
||||
BUS_WAKER.wake();
|
||||
}
|
||||
|
||||
if istr.wkup() {
|
||||
//trace!("USB IRQ: wkup");
|
||||
IRQ_RESUME.store(true, Ordering::Relaxed);
|
||||
regs.cntr().modify(|w| {
|
||||
w.set_fsusp(false);
|
||||
w.set_lpmode(false);
|
||||
});
|
||||
|
||||
// Write 0 to clear.
|
||||
let mut clear = regs::Istr(!0);
|
||||
clear.set_wkup(false);
|
||||
regs.istr().write_value(clear);
|
||||
|
||||
// Wake main thread.
|
||||
BUS_WAKER.wake();
|
||||
}
|
||||
|
||||
if istr.reset() {
|
||||
//trace!("USB IRQ: reset");
|
||||
IRQ_RESET.store(true, Ordering::Relaxed);
|
||||
|
||||
// Write 0 to clear.
|
||||
let mut clear = regs::Istr(!0);
|
||||
clear.set_reset(false);
|
||||
regs.istr().write_value(clear);
|
||||
|
||||
// Wake main thread.
|
||||
BUS_WAKER.wake();
|
||||
}
|
||||
|
||||
if istr.ctr() {
|
||||
let index = istr.ep_id() as usize;
|
||||
let mut epr = regs.epr(index).read();
|
||||
if epr.ctr_rx() {
|
||||
if index == 0 && epr.setup() {
|
||||
EP0_SETUP.store(true, Ordering::Relaxed);
|
||||
}
|
||||
//trace!("EP {} RX, setup={}", index, epr.setup());
|
||||
EP_OUT_WAKERS[index].wake();
|
||||
}
|
||||
if epr.ctr_tx() {
|
||||
//trace!("EP {} TX", index);
|
||||
EP_IN_WAKERS[index].wake();
|
||||
}
|
||||
epr.set_dtog_rx(false);
|
||||
epr.set_dtog_tx(false);
|
||||
epr.set_stat_rx(Stat(0));
|
||||
epr.set_stat_tx(Stat(0));
|
||||
epr.set_ctr_rx(!epr.ctr_rx());
|
||||
epr.set_ctr_tx(!epr.ctr_tx());
|
||||
regs.epr(index).write_value(epr);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
const EP_COUNT: usize = 8;
|
||||
|
||||
@ -168,14 +255,13 @@ pub struct Driver<'d, T: Instance> {
|
||||
impl<'d, T: Instance> Driver<'d, T> {
|
||||
pub fn new(
|
||||
_usb: impl Peripheral<P = T> + 'd,
|
||||
irq: impl Peripheral<P = T::Interrupt> + 'd,
|
||||
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
|
||||
dp: impl Peripheral<P = impl DpPin<T>> + 'd,
|
||||
dm: impl Peripheral<P = impl DmPin<T>> + 'd,
|
||||
) -> Self {
|
||||
into_ref!(irq, dp, dm);
|
||||
irq.set_handler(Self::on_interrupt);
|
||||
irq.unpend();
|
||||
irq.enable();
|
||||
into_ref!(dp, dm);
|
||||
unsafe { T::Interrupt::steal() }.unpend();
|
||||
unsafe { T::Interrupt::steal() }.enable();
|
||||
|
||||
let regs = T::regs();
|
||||
|
||||
@ -225,86 +311,6 @@ impl<'d, T: Instance> Driver<'d, T> {
|
||||
}
|
||||
}
|
||||
|
||||
fn on_interrupt(_: *mut ()) {
|
||||
unsafe {
|
||||
let regs = T::regs();
|
||||
//let x = regs.istr().read().0;
|
||||
//trace!("USB IRQ: {:08x}", x);
|
||||
|
||||
let istr = regs.istr().read();
|
||||
|
||||
if istr.susp() {
|
||||
//trace!("USB IRQ: susp");
|
||||
IRQ_SUSPEND.store(true, Ordering::Relaxed);
|
||||
regs.cntr().modify(|w| {
|
||||
w.set_fsusp(true);
|
||||
w.set_lpmode(true);
|
||||
});
|
||||
|
||||
// Write 0 to clear.
|
||||
let mut clear = regs::Istr(!0);
|
||||
clear.set_susp(false);
|
||||
regs.istr().write_value(clear);
|
||||
|
||||
// Wake main thread.
|
||||
BUS_WAKER.wake();
|
||||
}
|
||||
|
||||
if istr.wkup() {
|
||||
//trace!("USB IRQ: wkup");
|
||||
IRQ_RESUME.store(true, Ordering::Relaxed);
|
||||
regs.cntr().modify(|w| {
|
||||
w.set_fsusp(false);
|
||||
w.set_lpmode(false);
|
||||
});
|
||||
|
||||
// Write 0 to clear.
|
||||
let mut clear = regs::Istr(!0);
|
||||
clear.set_wkup(false);
|
||||
regs.istr().write_value(clear);
|
||||
|
||||
// Wake main thread.
|
||||
BUS_WAKER.wake();
|
||||
}
|
||||
|
||||
if istr.reset() {
|
||||
//trace!("USB IRQ: reset");
|
||||
IRQ_RESET.store(true, Ordering::Relaxed);
|
||||
|
||||
// Write 0 to clear.
|
||||
let mut clear = regs::Istr(!0);
|
||||
clear.set_reset(false);
|
||||
regs.istr().write_value(clear);
|
||||
|
||||
// Wake main thread.
|
||||
BUS_WAKER.wake();
|
||||
}
|
||||
|
||||
if istr.ctr() {
|
||||
let index = istr.ep_id() as usize;
|
||||
let mut epr = regs.epr(index).read();
|
||||
if epr.ctr_rx() {
|
||||
if index == 0 && epr.setup() {
|
||||
EP0_SETUP.store(true, Ordering::Relaxed);
|
||||
}
|
||||
//trace!("EP {} RX, setup={}", index, epr.setup());
|
||||
EP_OUT_WAKERS[index].wake();
|
||||
}
|
||||
if epr.ctr_tx() {
|
||||
//trace!("EP {} TX", index);
|
||||
EP_IN_WAKERS[index].wake();
|
||||
}
|
||||
epr.set_dtog_rx(false);
|
||||
epr.set_dtog_tx(false);
|
||||
epr.set_stat_rx(Stat(0));
|
||||
epr.set_stat_tx(Stat(0));
|
||||
epr.set_ctr_rx(!epr.ctr_rx());
|
||||
epr.set_ctr_tx(!epr.ctr_tx());
|
||||
regs.epr(index).write_value(epr);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
fn alloc_ep_mem(&mut self, len: u16) -> u16 {
|
||||
assert!(len as usize % USBRAM_ALIGN == 0);
|
||||
let addr = self.ep_mem_free;
|
||||
|
@ -4,7 +4,7 @@ use core::task::Poll;
|
||||
|
||||
use atomic_polyfill::{AtomicBool, AtomicU16, Ordering};
|
||||
use embassy_cortex_m::interrupt::InterruptExt;
|
||||
use embassy_hal_common::{into_ref, Peripheral, PeripheralRef};
|
||||
use embassy_hal_common::{into_ref, Peripheral};
|
||||
use embassy_sync::waitqueue::AtomicWaker;
|
||||
use embassy_usb_driver::{
|
||||
self, Direction, EndpointAddress, EndpointAllocError, EndpointError, EndpointIn, EndpointInfo, EndpointOut,
|
||||
@ -14,490 +14,18 @@ use futures::future::poll_fn;
|
||||
|
||||
use super::*;
|
||||
use crate::gpio::sealed::AFType;
|
||||
use crate::interrupt;
|
||||
use crate::pac::otg::{regs, vals};
|
||||
use crate::rcc::sealed::RccPeripheral;
|
||||
use crate::time::Hertz;
|
||||
|
||||
macro_rules! config_ulpi_pins {
|
||||
($($pin:ident),*) => {
|
||||
into_ref!($($pin),*);
|
||||
// NOTE(unsafe) Exclusive access to the registers
|
||||
critical_section::with(|_| unsafe {
|
||||
$(
|
||||
$pin.set_as_af($pin.af_num(), AFType::OutputPushPull);
|
||||
#[cfg(gpio_v2)]
|
||||
$pin.set_speed(crate::gpio::Speed::VeryHigh);
|
||||
)*
|
||||
})
|
||||
};
|
||||
/// Interrupt handler.
|
||||
pub struct InterruptHandler<T: Instance> {
|
||||
_phantom: PhantomData<T>,
|
||||
}
|
||||
|
||||
// From `synopsys-usb-otg` crate:
|
||||
// This calculation doesn't correspond to one in a Reference Manual.
|
||||
// In fact, the required number of words is higher than indicated in RM.
|
||||
// The following numbers are pessimistic and were figured out empirically.
|
||||
const RX_FIFO_EXTRA_SIZE_WORDS: u16 = 30;
|
||||
|
||||
/// USB PHY type
|
||||
#[derive(Copy, Clone, Debug, Eq, PartialEq)]
|
||||
pub enum PhyType {
|
||||
/// Internal Full-Speed PHY
|
||||
///
|
||||
/// Available on most High-Speed peripherals.
|
||||
InternalFullSpeed,
|
||||
/// Internal High-Speed PHY
|
||||
///
|
||||
/// Available on a few STM32 chips.
|
||||
InternalHighSpeed,
|
||||
/// External ULPI High-Speed PHY
|
||||
ExternalHighSpeed,
|
||||
}
|
||||
|
||||
impl PhyType {
|
||||
pub fn internal(&self) -> bool {
|
||||
match self {
|
||||
PhyType::InternalFullSpeed | PhyType::InternalHighSpeed => true,
|
||||
PhyType::ExternalHighSpeed => false,
|
||||
}
|
||||
}
|
||||
|
||||
pub fn high_speed(&self) -> bool {
|
||||
match self {
|
||||
PhyType::InternalFullSpeed => false,
|
||||
PhyType::ExternalHighSpeed | PhyType::InternalHighSpeed => true,
|
||||
}
|
||||
}
|
||||
|
||||
pub fn to_dspd(&self) -> vals::Dspd {
|
||||
match self {
|
||||
PhyType::InternalFullSpeed => vals::Dspd::FULL_SPEED_INTERNAL,
|
||||
PhyType::InternalHighSpeed => vals::Dspd::HIGH_SPEED,
|
||||
PhyType::ExternalHighSpeed => vals::Dspd::HIGH_SPEED,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// Indicates that [State::ep_out_buffers] is empty.
|
||||
const EP_OUT_BUFFER_EMPTY: u16 = u16::MAX;
|
||||
|
||||
pub struct State<const EP_COUNT: usize> {
|
||||
/// Holds received SETUP packets. Available if [State::ep0_setup_ready] is true.
|
||||
ep0_setup_data: UnsafeCell<[u8; 8]>,
|
||||
ep0_setup_ready: AtomicBool,
|
||||
ep_in_wakers: [AtomicWaker; EP_COUNT],
|
||||
ep_out_wakers: [AtomicWaker; EP_COUNT],
|
||||
/// RX FIFO is shared so extra buffers are needed to dequeue all data without waiting on each endpoint.
|
||||
/// Buffers are ready when associated [State::ep_out_size] != [EP_OUT_BUFFER_EMPTY].
|
||||
ep_out_buffers: [UnsafeCell<*mut u8>; EP_COUNT],
|
||||
ep_out_size: [AtomicU16; EP_COUNT],
|
||||
bus_waker: AtomicWaker,
|
||||
}
|
||||
|
||||
unsafe impl<const EP_COUNT: usize> Send for State<EP_COUNT> {}
|
||||
unsafe impl<const EP_COUNT: usize> Sync for State<EP_COUNT> {}
|
||||
|
||||
impl<const EP_COUNT: usize> State<EP_COUNT> {
|
||||
pub const fn new() -> Self {
|
||||
const NEW_AW: AtomicWaker = AtomicWaker::new();
|
||||
const NEW_BUF: UnsafeCell<*mut u8> = UnsafeCell::new(0 as _);
|
||||
const NEW_SIZE: AtomicU16 = AtomicU16::new(EP_OUT_BUFFER_EMPTY);
|
||||
|
||||
Self {
|
||||
ep0_setup_data: UnsafeCell::new([0u8; 8]),
|
||||
ep0_setup_ready: AtomicBool::new(false),
|
||||
ep_in_wakers: [NEW_AW; EP_COUNT],
|
||||
ep_out_wakers: [NEW_AW; EP_COUNT],
|
||||
ep_out_buffers: [NEW_BUF; EP_COUNT],
|
||||
ep_out_size: [NEW_SIZE; EP_COUNT],
|
||||
bus_waker: NEW_AW,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#[derive(Debug, Clone, Copy)]
|
||||
struct EndpointData {
|
||||
ep_type: EndpointType,
|
||||
max_packet_size: u16,
|
||||
fifo_size_words: u16,
|
||||
}
|
||||
|
||||
pub struct Driver<'d, T: Instance> {
|
||||
phantom: PhantomData<&'d mut T>,
|
||||
irq: PeripheralRef<'d, T::Interrupt>,
|
||||
ep_in: [Option<EndpointData>; MAX_EP_COUNT],
|
||||
ep_out: [Option<EndpointData>; MAX_EP_COUNT],
|
||||
ep_out_buffer: &'d mut [u8],
|
||||
ep_out_buffer_offset: usize,
|
||||
phy_type: PhyType,
|
||||
}
|
||||
|
||||
impl<'d, T: Instance> Driver<'d, T> {
|
||||
/// Initializes USB OTG peripheral with internal Full-Speed PHY.
|
||||
///
|
||||
/// # Arguments
|
||||
///
|
||||
/// * `ep_out_buffer` - An internal buffer used to temporarily store recevied packets.
|
||||
/// Must be large enough to fit all OUT endpoint max packet sizes.
|
||||
/// Endpoint allocation will fail if it is too small.
|
||||
pub fn new_fs(
|
||||
_peri: impl Peripheral<P = T> + 'd,
|
||||
irq: impl Peripheral<P = T::Interrupt> + 'd,
|
||||
dp: impl Peripheral<P = impl DpPin<T>> + 'd,
|
||||
dm: impl Peripheral<P = impl DmPin<T>> + 'd,
|
||||
ep_out_buffer: &'d mut [u8],
|
||||
) -> Self {
|
||||
into_ref!(dp, dm, irq);
|
||||
|
||||
unsafe {
|
||||
dp.set_as_af(dp.af_num(), AFType::OutputPushPull);
|
||||
dm.set_as_af(dm.af_num(), AFType::OutputPushPull);
|
||||
}
|
||||
|
||||
Self {
|
||||
phantom: PhantomData,
|
||||
irq,
|
||||
ep_in: [None; MAX_EP_COUNT],
|
||||
ep_out: [None; MAX_EP_COUNT],
|
||||
ep_out_buffer,
|
||||
ep_out_buffer_offset: 0,
|
||||
phy_type: PhyType::InternalFullSpeed,
|
||||
}
|
||||
}
|
||||
|
||||
/// Initializes USB OTG peripheral with external High-Speed PHY.
|
||||
///
|
||||
/// # Arguments
|
||||
///
|
||||
/// * `ep_out_buffer` - An internal buffer used to temporarily store recevied packets.
|
||||
/// Must be large enough to fit all OUT endpoint max packet sizes.
|
||||
/// Endpoint allocation will fail if it is too small.
|
||||
pub fn new_hs_ulpi(
|
||||
_peri: impl Peripheral<P = T> + 'd,
|
||||
irq: impl Peripheral<P = T::Interrupt> + 'd,
|
||||
ulpi_clk: impl Peripheral<P = impl UlpiClkPin<T>> + 'd,
|
||||
ulpi_dir: impl Peripheral<P = impl UlpiDirPin<T>> + 'd,
|
||||
ulpi_nxt: impl Peripheral<P = impl UlpiNxtPin<T>> + 'd,
|
||||
ulpi_stp: impl Peripheral<P = impl UlpiStpPin<T>> + 'd,
|
||||
ulpi_d0: impl Peripheral<P = impl UlpiD0Pin<T>> + 'd,
|
||||
ulpi_d1: impl Peripheral<P = impl UlpiD1Pin<T>> + 'd,
|
||||
ulpi_d2: impl Peripheral<P = impl UlpiD2Pin<T>> + 'd,
|
||||
ulpi_d3: impl Peripheral<P = impl UlpiD3Pin<T>> + 'd,
|
||||
ulpi_d4: impl Peripheral<P = impl UlpiD4Pin<T>> + 'd,
|
||||
ulpi_d5: impl Peripheral<P = impl UlpiD5Pin<T>> + 'd,
|
||||
ulpi_d6: impl Peripheral<P = impl UlpiD6Pin<T>> + 'd,
|
||||
ulpi_d7: impl Peripheral<P = impl UlpiD7Pin<T>> + 'd,
|
||||
ep_out_buffer: &'d mut [u8],
|
||||
) -> Self {
|
||||
assert!(T::HIGH_SPEED == true, "Peripheral is not capable of high-speed USB");
|
||||
|
||||
config_ulpi_pins!(
|
||||
ulpi_clk, ulpi_dir, ulpi_nxt, ulpi_stp, ulpi_d0, ulpi_d1, ulpi_d2, ulpi_d3, ulpi_d4, ulpi_d5, ulpi_d6,
|
||||
ulpi_d7
|
||||
);
|
||||
|
||||
into_ref!(irq);
|
||||
|
||||
Self {
|
||||
phantom: PhantomData,
|
||||
irq,
|
||||
ep_in: [None; MAX_EP_COUNT],
|
||||
ep_out: [None; MAX_EP_COUNT],
|
||||
ep_out_buffer,
|
||||
ep_out_buffer_offset: 0,
|
||||
phy_type: PhyType::ExternalHighSpeed,
|
||||
}
|
||||
}
|
||||
|
||||
// Returns total amount of words (u32) allocated in dedicated FIFO
|
||||
fn allocated_fifo_words(&self) -> u16 {
|
||||
RX_FIFO_EXTRA_SIZE_WORDS + ep_fifo_size(&self.ep_out) + ep_fifo_size(&self.ep_in)
|
||||
}
|
||||
|
||||
fn alloc_endpoint<D: Dir>(
|
||||
&mut self,
|
||||
ep_type: EndpointType,
|
||||
max_packet_size: u16,
|
||||
interval_ms: u8,
|
||||
) -> Result<Endpoint<'d, T, D>, EndpointAllocError> {
|
||||
trace!(
|
||||
"allocating type={:?} mps={:?} interval_ms={}, dir={:?}",
|
||||
ep_type,
|
||||
max_packet_size,
|
||||
interval_ms,
|
||||
D::dir()
|
||||
);
|
||||
|
||||
if D::dir() == Direction::Out {
|
||||
if self.ep_out_buffer_offset + max_packet_size as usize >= self.ep_out_buffer.len() {
|
||||
error!("Not enough endpoint out buffer capacity");
|
||||
return Err(EndpointAllocError);
|
||||
}
|
||||
};
|
||||
|
||||
let fifo_size_words = match D::dir() {
|
||||
Direction::Out => (max_packet_size + 3) / 4,
|
||||
// INEPTXFD requires minimum size of 16 words
|
||||
Direction::In => u16::max((max_packet_size + 3) / 4, 16),
|
||||
};
|
||||
|
||||
if fifo_size_words + self.allocated_fifo_words() > T::FIFO_DEPTH_WORDS {
|
||||
error!("Not enough FIFO capacity");
|
||||
return Err(EndpointAllocError);
|
||||
}
|
||||
|
||||
let eps = match D::dir() {
|
||||
Direction::Out => &mut self.ep_out,
|
||||
Direction::In => &mut self.ep_in,
|
||||
};
|
||||
|
||||
// Find free endpoint slot
|
||||
let slot = eps.iter_mut().enumerate().find(|(i, ep)| {
|
||||
if *i == 0 && ep_type != EndpointType::Control {
|
||||
// reserved for control pipe
|
||||
false
|
||||
} else {
|
||||
ep.is_none()
|
||||
}
|
||||
});
|
||||
|
||||
let index = match slot {
|
||||
Some((index, ep)) => {
|
||||
*ep = Some(EndpointData {
|
||||
ep_type,
|
||||
max_packet_size,
|
||||
fifo_size_words,
|
||||
});
|
||||
index
|
||||
}
|
||||
None => {
|
||||
error!("No free endpoints available");
|
||||
return Err(EndpointAllocError);
|
||||
}
|
||||
};
|
||||
|
||||
trace!(" index={}", index);
|
||||
|
||||
if D::dir() == Direction::Out {
|
||||
// Buffer capacity check was done above, now allocation cannot fail
|
||||
unsafe {
|
||||
*T::state().ep_out_buffers[index].get() =
|
||||
self.ep_out_buffer.as_mut_ptr().offset(self.ep_out_buffer_offset as _);
|
||||
}
|
||||
self.ep_out_buffer_offset += max_packet_size as usize;
|
||||
}
|
||||
|
||||
Ok(Endpoint {
|
||||
_phantom: PhantomData,
|
||||
info: EndpointInfo {
|
||||
addr: EndpointAddress::from_parts(index, D::dir()),
|
||||
ep_type,
|
||||
max_packet_size,
|
||||
interval_ms,
|
||||
},
|
||||
})
|
||||
}
|
||||
}
|
||||
|
||||
impl<'d, T: Instance> embassy_usb_driver::Driver<'d> for Driver<'d, T> {
|
||||
type EndpointOut = Endpoint<'d, T, Out>;
|
||||
type EndpointIn = Endpoint<'d, T, In>;
|
||||
type ControlPipe = ControlPipe<'d, T>;
|
||||
type Bus = Bus<'d, T>;
|
||||
|
||||
fn alloc_endpoint_in(
|
||||
&mut self,
|
||||
ep_type: EndpointType,
|
||||
max_packet_size: u16,
|
||||
interval_ms: u8,
|
||||
) -> Result<Self::EndpointIn, EndpointAllocError> {
|
||||
self.alloc_endpoint(ep_type, max_packet_size, interval_ms)
|
||||
}
|
||||
|
||||
fn alloc_endpoint_out(
|
||||
&mut self,
|
||||
ep_type: EndpointType,
|
||||
max_packet_size: u16,
|
||||
interval_ms: u8,
|
||||
) -> Result<Self::EndpointOut, EndpointAllocError> {
|
||||
self.alloc_endpoint(ep_type, max_packet_size, interval_ms)
|
||||
}
|
||||
|
||||
fn start(mut self, control_max_packet_size: u16) -> (Self::Bus, Self::ControlPipe) {
|
||||
let ep_out = self
|
||||
.alloc_endpoint(EndpointType::Control, control_max_packet_size, 0)
|
||||
.unwrap();
|
||||
let ep_in = self
|
||||
.alloc_endpoint(EndpointType::Control, control_max_packet_size, 0)
|
||||
.unwrap();
|
||||
assert_eq!(ep_out.info.addr.index(), 0);
|
||||
assert_eq!(ep_in.info.addr.index(), 0);
|
||||
|
||||
trace!("start");
|
||||
|
||||
(
|
||||
Bus {
|
||||
phantom: PhantomData,
|
||||
irq: self.irq,
|
||||
ep_in: self.ep_in,
|
||||
ep_out: self.ep_out,
|
||||
phy_type: self.phy_type,
|
||||
enabled: false,
|
||||
},
|
||||
ControlPipe {
|
||||
_phantom: PhantomData,
|
||||
max_packet_size: control_max_packet_size,
|
||||
ep_out,
|
||||
ep_in,
|
||||
},
|
||||
)
|
||||
}
|
||||
}
|
||||
|
||||
pub struct Bus<'d, T: Instance> {
|
||||
phantom: PhantomData<&'d mut T>,
|
||||
irq: PeripheralRef<'d, T::Interrupt>,
|
||||
ep_in: [Option<EndpointData>; MAX_EP_COUNT],
|
||||
ep_out: [Option<EndpointData>; MAX_EP_COUNT],
|
||||
phy_type: PhyType,
|
||||
enabled: bool,
|
||||
}
|
||||
|
||||
impl<'d, T: Instance> Bus<'d, T> {
|
||||
fn restore_irqs() {
|
||||
// SAFETY: atomic write
|
||||
unsafe {
|
||||
T::regs().gintmsk().write(|w| {
|
||||
w.set_usbrst(true);
|
||||
w.set_enumdnem(true);
|
||||
w.set_usbsuspm(true);
|
||||
w.set_wuim(true);
|
||||
w.set_iepint(true);
|
||||
w.set_oepint(true);
|
||||
w.set_rxflvlm(true);
|
||||
});
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl<'d, T: Instance> Bus<'d, T> {
|
||||
fn init_fifo(&mut self) {
|
||||
trace!("init_fifo");
|
||||
|
||||
let r = T::regs();
|
||||
|
||||
// Configure RX fifo size. All endpoints share the same FIFO area.
|
||||
let rx_fifo_size_words = RX_FIFO_EXTRA_SIZE_WORDS + ep_fifo_size(&self.ep_out);
|
||||
trace!("configuring rx fifo size={}", rx_fifo_size_words);
|
||||
|
||||
// SAFETY: register is exclusive to `Bus` with `&mut self`
|
||||
unsafe { r.grxfsiz().modify(|w| w.set_rxfd(rx_fifo_size_words)) };
|
||||
|
||||
// Configure TX (USB in direction) fifo size for each endpoint
|
||||
let mut fifo_top = rx_fifo_size_words;
|
||||
for i in 0..T::ENDPOINT_COUNT {
|
||||
if let Some(ep) = self.ep_in[i] {
|
||||
trace!(
|
||||
"configuring tx fifo ep={}, offset={}, size={}",
|
||||
i,
|
||||
fifo_top,
|
||||
ep.fifo_size_words
|
||||
);
|
||||
|
||||
let dieptxf = if i == 0 { r.dieptxf0() } else { r.dieptxf(i - 1) };
|
||||
|
||||
// SAFETY: register is exclusive to `Bus` with `&mut self`
|
||||
unsafe {
|
||||
dieptxf.write(|w| {
|
||||
w.set_fd(ep.fifo_size_words);
|
||||
w.set_sa(fifo_top);
|
||||
});
|
||||
}
|
||||
|
||||
fifo_top += ep.fifo_size_words;
|
||||
}
|
||||
}
|
||||
|
||||
assert!(
|
||||
fifo_top <= T::FIFO_DEPTH_WORDS,
|
||||
"FIFO allocations exceeded maximum capacity"
|
||||
);
|
||||
}
|
||||
|
||||
fn configure_endpoints(&mut self) {
|
||||
trace!("configure_endpoints");
|
||||
|
||||
let r = T::regs();
|
||||
|
||||
// Configure IN endpoints
|
||||
for (index, ep) in self.ep_in.iter().enumerate() {
|
||||
if let Some(ep) = ep {
|
||||
// SAFETY: DIEPCTL is shared with `Endpoint` so critical section is needed for RMW
|
||||
critical_section::with(|_| unsafe {
|
||||
r.diepctl(index).write(|w| {
|
||||
if index == 0 {
|
||||
w.set_mpsiz(ep0_mpsiz(ep.max_packet_size));
|
||||
} else {
|
||||
w.set_mpsiz(ep.max_packet_size);
|
||||
w.set_eptyp(to_eptyp(ep.ep_type));
|
||||
w.set_sd0pid_sevnfrm(true);
|
||||
}
|
||||
});
|
||||
});
|
||||
}
|
||||
}
|
||||
|
||||
// Configure OUT endpoints
|
||||
for (index, ep) in self.ep_out.iter().enumerate() {
|
||||
if let Some(ep) = ep {
|
||||
// SAFETY: DOEPCTL/DOEPTSIZ is shared with `Endpoint` so critical section is needed for RMW
|
||||
critical_section::with(|_| unsafe {
|
||||
r.doepctl(index).write(|w| {
|
||||
if index == 0 {
|
||||
w.set_mpsiz(ep0_mpsiz(ep.max_packet_size));
|
||||
} else {
|
||||
w.set_mpsiz(ep.max_packet_size);
|
||||
w.set_eptyp(to_eptyp(ep.ep_type));
|
||||
w.set_sd0pid_sevnfrm(true);
|
||||
}
|
||||
});
|
||||
|
||||
r.doeptsiz(index).modify(|w| {
|
||||
w.set_xfrsiz(ep.max_packet_size as _);
|
||||
if index == 0 {
|
||||
w.set_rxdpid_stupcnt(1);
|
||||
} else {
|
||||
w.set_pktcnt(1);
|
||||
}
|
||||
});
|
||||
});
|
||||
}
|
||||
}
|
||||
|
||||
// Enable IRQs for allocated endpoints
|
||||
// SAFETY: register is exclusive to `Bus` with `&mut self`
|
||||
unsafe {
|
||||
r.daintmsk().modify(|w| {
|
||||
w.set_iepm(ep_irq_mask(&self.ep_in));
|
||||
// OUT interrupts not used, handled in RXFLVL
|
||||
// w.set_oepm(ep_irq_mask(&self.ep_out));
|
||||
});
|
||||
}
|
||||
}
|
||||
|
||||
fn disable(&mut self) {
|
||||
self.irq.disable();
|
||||
self.irq.remove_handler();
|
||||
|
||||
<T as RccPeripheral>::disable();
|
||||
|
||||
#[cfg(stm32l4)]
|
||||
unsafe {
|
||||
crate::pac::PWR.cr2().modify(|w| w.set_usv(false));
|
||||
// Cannot disable PWR, because other peripherals might be using it
|
||||
}
|
||||
}
|
||||
|
||||
fn on_interrupt(_: *mut ()) {
|
||||
impl<T: Instance> interrupt::Handler<T::Interrupt> for InterruptHandler<T> {
|
||||
unsafe fn on_interrupt() {
|
||||
trace!("irq");
|
||||
let r = T::regs();
|
||||
let state = T::state();
|
||||
@ -641,6 +169,478 @@ impl<'d, T: Instance> Bus<'d, T> {
|
||||
}
|
||||
}
|
||||
|
||||
macro_rules! config_ulpi_pins {
|
||||
($($pin:ident),*) => {
|
||||
into_ref!($($pin),*);
|
||||
// NOTE(unsafe) Exclusive access to the registers
|
||||
critical_section::with(|_| unsafe {
|
||||
$(
|
||||
$pin.set_as_af($pin.af_num(), AFType::OutputPushPull);
|
||||
#[cfg(gpio_v2)]
|
||||
$pin.set_speed(crate::gpio::Speed::VeryHigh);
|
||||
)*
|
||||
})
|
||||
};
|
||||
}
|
||||
|
||||
// From `synopsys-usb-otg` crate:
|
||||
// This calculation doesn't correspond to one in a Reference Manual.
|
||||
// In fact, the required number of words is higher than indicated in RM.
|
||||
// The following numbers are pessimistic and were figured out empirically.
|
||||
const RX_FIFO_EXTRA_SIZE_WORDS: u16 = 30;
|
||||
|
||||
/// USB PHY type
|
||||
#[derive(Copy, Clone, Debug, Eq, PartialEq)]
|
||||
pub enum PhyType {
|
||||
/// Internal Full-Speed PHY
|
||||
///
|
||||
/// Available on most High-Speed peripherals.
|
||||
InternalFullSpeed,
|
||||
/// Internal High-Speed PHY
|
||||
///
|
||||
/// Available on a few STM32 chips.
|
||||
InternalHighSpeed,
|
||||
/// External ULPI High-Speed PHY
|
||||
ExternalHighSpeed,
|
||||
}
|
||||
|
||||
impl PhyType {
|
||||
pub fn internal(&self) -> bool {
|
||||
match self {
|
||||
PhyType::InternalFullSpeed | PhyType::InternalHighSpeed => true,
|
||||
PhyType::ExternalHighSpeed => false,
|
||||
}
|
||||
}
|
||||
|
||||
pub fn high_speed(&self) -> bool {
|
||||
match self {
|
||||
PhyType::InternalFullSpeed => false,
|
||||
PhyType::ExternalHighSpeed | PhyType::InternalHighSpeed => true,
|
||||
}
|
||||
}
|
||||
|
||||
pub fn to_dspd(&self) -> vals::Dspd {
|
||||
match self {
|
||||
PhyType::InternalFullSpeed => vals::Dspd::FULL_SPEED_INTERNAL,
|
||||
PhyType::InternalHighSpeed => vals::Dspd::HIGH_SPEED,
|
||||
PhyType::ExternalHighSpeed => vals::Dspd::HIGH_SPEED,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// Indicates that [State::ep_out_buffers] is empty.
|
||||
const EP_OUT_BUFFER_EMPTY: u16 = u16::MAX;
|
||||
|
||||
pub struct State<const EP_COUNT: usize> {
|
||||
/// Holds received SETUP packets. Available if [State::ep0_setup_ready] is true.
|
||||
ep0_setup_data: UnsafeCell<[u8; 8]>,
|
||||
ep0_setup_ready: AtomicBool,
|
||||
ep_in_wakers: [AtomicWaker; EP_COUNT],
|
||||
ep_out_wakers: [AtomicWaker; EP_COUNT],
|
||||
/// RX FIFO is shared so extra buffers are needed to dequeue all data without waiting on each endpoint.
|
||||
/// Buffers are ready when associated [State::ep_out_size] != [EP_OUT_BUFFER_EMPTY].
|
||||
ep_out_buffers: [UnsafeCell<*mut u8>; EP_COUNT],
|
||||
ep_out_size: [AtomicU16; EP_COUNT],
|
||||
bus_waker: AtomicWaker,
|
||||
}
|
||||
|
||||
unsafe impl<const EP_COUNT: usize> Send for State<EP_COUNT> {}
|
||||
unsafe impl<const EP_COUNT: usize> Sync for State<EP_COUNT> {}
|
||||
|
||||
impl<const EP_COUNT: usize> State<EP_COUNT> {
|
||||
pub const fn new() -> Self {
|
||||
const NEW_AW: AtomicWaker = AtomicWaker::new();
|
||||
const NEW_BUF: UnsafeCell<*mut u8> = UnsafeCell::new(0 as _);
|
||||
const NEW_SIZE: AtomicU16 = AtomicU16::new(EP_OUT_BUFFER_EMPTY);
|
||||
|
||||
Self {
|
||||
ep0_setup_data: UnsafeCell::new([0u8; 8]),
|
||||
ep0_setup_ready: AtomicBool::new(false),
|
||||
ep_in_wakers: [NEW_AW; EP_COUNT],
|
||||
ep_out_wakers: [NEW_AW; EP_COUNT],
|
||||
ep_out_buffers: [NEW_BUF; EP_COUNT],
|
||||
ep_out_size: [NEW_SIZE; EP_COUNT],
|
||||
bus_waker: NEW_AW,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#[derive(Debug, Clone, Copy)]
|
||||
struct EndpointData {
|
||||
ep_type: EndpointType,
|
||||
max_packet_size: u16,
|
||||
fifo_size_words: u16,
|
||||
}
|
||||
|
||||
pub struct Driver<'d, T: Instance> {
|
||||
phantom: PhantomData<&'d mut T>,
|
||||
ep_in: [Option<EndpointData>; MAX_EP_COUNT],
|
||||
ep_out: [Option<EndpointData>; MAX_EP_COUNT],
|
||||
ep_out_buffer: &'d mut [u8],
|
||||
ep_out_buffer_offset: usize,
|
||||
phy_type: PhyType,
|
||||
}
|
||||
|
||||
impl<'d, T: Instance> Driver<'d, T> {
|
||||
/// Initializes USB OTG peripheral with internal Full-Speed PHY.
|
||||
///
|
||||
/// # Arguments
|
||||
///
|
||||
/// * `ep_out_buffer` - An internal buffer used to temporarily store recevied packets.
|
||||
/// Must be large enough to fit all OUT endpoint max packet sizes.
|
||||
/// Endpoint allocation will fail if it is too small.
|
||||
pub fn new_fs(
|
||||
_peri: impl Peripheral<P = T> + 'd,
|
||||
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
|
||||
dp: impl Peripheral<P = impl DpPin<T>> + 'd,
|
||||
dm: impl Peripheral<P = impl DmPin<T>> + 'd,
|
||||
ep_out_buffer: &'d mut [u8],
|
||||
) -> Self {
|
||||
into_ref!(dp, dm);
|
||||
|
||||
unsafe {
|
||||
dp.set_as_af(dp.af_num(), AFType::OutputPushPull);
|
||||
dm.set_as_af(dm.af_num(), AFType::OutputPushPull);
|
||||
}
|
||||
|
||||
Self {
|
||||
phantom: PhantomData,
|
||||
ep_in: [None; MAX_EP_COUNT],
|
||||
ep_out: [None; MAX_EP_COUNT],
|
||||
ep_out_buffer,
|
||||
ep_out_buffer_offset: 0,
|
||||
phy_type: PhyType::InternalFullSpeed,
|
||||
}
|
||||
}
|
||||
|
||||
/// Initializes USB OTG peripheral with external High-Speed PHY.
|
||||
///
|
||||
/// # Arguments
|
||||
///
|
||||
/// * `ep_out_buffer` - An internal buffer used to temporarily store recevied packets.
|
||||
/// Must be large enough to fit all OUT endpoint max packet sizes.
|
||||
/// Endpoint allocation will fail if it is too small.
|
||||
pub fn new_hs_ulpi(
|
||||
_peri: impl Peripheral<P = T> + 'd,
|
||||
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
|
||||
ulpi_clk: impl Peripheral<P = impl UlpiClkPin<T>> + 'd,
|
||||
ulpi_dir: impl Peripheral<P = impl UlpiDirPin<T>> + 'd,
|
||||
ulpi_nxt: impl Peripheral<P = impl UlpiNxtPin<T>> + 'd,
|
||||
ulpi_stp: impl Peripheral<P = impl UlpiStpPin<T>> + 'd,
|
||||
ulpi_d0: impl Peripheral<P = impl UlpiD0Pin<T>> + 'd,
|
||||
ulpi_d1: impl Peripheral<P = impl UlpiD1Pin<T>> + 'd,
|
||||
ulpi_d2: impl Peripheral<P = impl UlpiD2Pin<T>> + 'd,
|
||||
ulpi_d3: impl Peripheral<P = impl UlpiD3Pin<T>> + 'd,
|
||||
ulpi_d4: impl Peripheral<P = impl UlpiD4Pin<T>> + 'd,
|
||||
ulpi_d5: impl Peripheral<P = impl UlpiD5Pin<T>> + 'd,
|
||||
ulpi_d6: impl Peripheral<P = impl UlpiD6Pin<T>> + 'd,
|
||||
ulpi_d7: impl Peripheral<P = impl UlpiD7Pin<T>> + 'd,
|
||||
ep_out_buffer: &'d mut [u8],
|
||||
) -> Self {
|
||||
assert!(T::HIGH_SPEED == true, "Peripheral is not capable of high-speed USB");
|
||||
|
||||
config_ulpi_pins!(
|
||||
ulpi_clk, ulpi_dir, ulpi_nxt, ulpi_stp, ulpi_d0, ulpi_d1, ulpi_d2, ulpi_d3, ulpi_d4, ulpi_d5, ulpi_d6,
|
||||
ulpi_d7
|
||||
);
|
||||
|
||||
Self {
|
||||
phantom: PhantomData,
|
||||
ep_in: [None; MAX_EP_COUNT],
|
||||
ep_out: [None; MAX_EP_COUNT],
|
||||
ep_out_buffer,
|
||||
ep_out_buffer_offset: 0,
|
||||
phy_type: PhyType::ExternalHighSpeed,
|
||||
}
|
||||
}
|
||||
|
||||
// Returns total amount of words (u32) allocated in dedicated FIFO
|
||||
fn allocated_fifo_words(&self) -> u16 {
|
||||
RX_FIFO_EXTRA_SIZE_WORDS + ep_fifo_size(&self.ep_out) + ep_fifo_size(&self.ep_in)
|
||||
}
|
||||
|
||||
fn alloc_endpoint<D: Dir>(
|
||||
&mut self,
|
||||
ep_type: EndpointType,
|
||||
max_packet_size: u16,
|
||||
interval_ms: u8,
|
||||
) -> Result<Endpoint<'d, T, D>, EndpointAllocError> {
|
||||
trace!(
|
||||
"allocating type={:?} mps={:?} interval_ms={}, dir={:?}",
|
||||
ep_type,
|
||||
max_packet_size,
|
||||
interval_ms,
|
||||
D::dir()
|
||||
);
|
||||
|
||||
if D::dir() == Direction::Out {
|
||||
if self.ep_out_buffer_offset + max_packet_size as usize >= self.ep_out_buffer.len() {
|
||||
error!("Not enough endpoint out buffer capacity");
|
||||
return Err(EndpointAllocError);
|
||||
}
|
||||
};
|
||||
|
||||
let fifo_size_words = match D::dir() {
|
||||
Direction::Out => (max_packet_size + 3) / 4,
|
||||
// INEPTXFD requires minimum size of 16 words
|
||||
Direction::In => u16::max((max_packet_size + 3) / 4, 16),
|
||||
};
|
||||
|
||||
if fifo_size_words + self.allocated_fifo_words() > T::FIFO_DEPTH_WORDS {
|
||||
error!("Not enough FIFO capacity");
|
||||
return Err(EndpointAllocError);
|
||||
}
|
||||
|
||||
let eps = match D::dir() {
|
||||
Direction::Out => &mut self.ep_out,
|
||||
Direction::In => &mut self.ep_in,
|
||||
};
|
||||
|
||||
// Find free endpoint slot
|
||||
let slot = eps.iter_mut().enumerate().find(|(i, ep)| {
|
||||
if *i == 0 && ep_type != EndpointType::Control {
|
||||
// reserved for control pipe
|
||||
false
|
||||
} else {
|
||||
ep.is_none()
|
||||
}
|
||||
});
|
||||
|
||||
let index = match slot {
|
||||
Some((index, ep)) => {
|
||||
*ep = Some(EndpointData {
|
||||
ep_type,
|
||||
max_packet_size,
|
||||
fifo_size_words,
|
||||
});
|
||||
index
|
||||
}
|
||||
None => {
|
||||
error!("No free endpoints available");
|
||||
return Err(EndpointAllocError);
|
||||
}
|
||||
};
|
||||
|
||||
trace!(" index={}", index);
|
||||
|
||||
if D::dir() == Direction::Out {
|
||||
// Buffer capacity check was done above, now allocation cannot fail
|
||||
unsafe {
|
||||
*T::state().ep_out_buffers[index].get() =
|
||||
self.ep_out_buffer.as_mut_ptr().offset(self.ep_out_buffer_offset as _);
|
||||
}
|
||||
self.ep_out_buffer_offset += max_packet_size as usize;
|
||||
}
|
||||
|
||||
Ok(Endpoint {
|
||||
_phantom: PhantomData,
|
||||
info: EndpointInfo {
|
||||
addr: EndpointAddress::from_parts(index, D::dir()),
|
||||
ep_type,
|
||||
max_packet_size,
|
||||
interval_ms,
|
||||
},
|
||||
})
|
||||
}
|
||||
}
|
||||
|
||||
impl<'d, T: Instance> embassy_usb_driver::Driver<'d> for Driver<'d, T> {
|
||||
type EndpointOut = Endpoint<'d, T, Out>;
|
||||
type EndpointIn = Endpoint<'d, T, In>;
|
||||
type ControlPipe = ControlPipe<'d, T>;
|
||||
type Bus = Bus<'d, T>;
|
||||
|
||||
fn alloc_endpoint_in(
|
||||
&mut self,
|
||||
ep_type: EndpointType,
|
||||
max_packet_size: u16,
|
||||
interval_ms: u8,
|
||||
) -> Result<Self::EndpointIn, EndpointAllocError> {
|
||||
self.alloc_endpoint(ep_type, max_packet_size, interval_ms)
|
||||
}
|
||||
|
||||
fn alloc_endpoint_out(
|
||||
&mut self,
|
||||
ep_type: EndpointType,
|
||||
max_packet_size: u16,
|
||||
interval_ms: u8,
|
||||
) -> Result<Self::EndpointOut, EndpointAllocError> {
|
||||
self.alloc_endpoint(ep_type, max_packet_size, interval_ms)
|
||||
}
|
||||
|
||||
fn start(mut self, control_max_packet_size: u16) -> (Self::Bus, Self::ControlPipe) {
|
||||
let ep_out = self
|
||||
.alloc_endpoint(EndpointType::Control, control_max_packet_size, 0)
|
||||
.unwrap();
|
||||
let ep_in = self
|
||||
.alloc_endpoint(EndpointType::Control, control_max_packet_size, 0)
|
||||
.unwrap();
|
||||
assert_eq!(ep_out.info.addr.index(), 0);
|
||||
assert_eq!(ep_in.info.addr.index(), 0);
|
||||
|
||||
trace!("start");
|
||||
|
||||
(
|
||||
Bus {
|
||||
phantom: PhantomData,
|
||||
ep_in: self.ep_in,
|
||||
ep_out: self.ep_out,
|
||||
phy_type: self.phy_type,
|
||||
enabled: false,
|
||||
},
|
||||
ControlPipe {
|
||||
_phantom: PhantomData,
|
||||
max_packet_size: control_max_packet_size,
|
||||
ep_out,
|
||||
ep_in,
|
||||
},
|
||||
)
|
||||
}
|
||||
}
|
||||
|
||||
pub struct Bus<'d, T: Instance> {
|
||||
phantom: PhantomData<&'d mut T>,
|
||||
ep_in: [Option<EndpointData>; MAX_EP_COUNT],
|
||||
ep_out: [Option<EndpointData>; MAX_EP_COUNT],
|
||||
phy_type: PhyType,
|
||||
enabled: bool,
|
||||
}
|
||||
|
||||
impl<'d, T: Instance> Bus<'d, T> {
|
||||
fn restore_irqs() {
|
||||
// SAFETY: atomic write
|
||||
unsafe {
|
||||
T::regs().gintmsk().write(|w| {
|
||||
w.set_usbrst(true);
|
||||
w.set_enumdnem(true);
|
||||
w.set_usbsuspm(true);
|
||||
w.set_wuim(true);
|
||||
w.set_iepint(true);
|
||||
w.set_oepint(true);
|
||||
w.set_rxflvlm(true);
|
||||
});
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl<'d, T: Instance> Bus<'d, T> {
|
||||
fn init_fifo(&mut self) {
|
||||
trace!("init_fifo");
|
||||
|
||||
let r = T::regs();
|
||||
|
||||
// Configure RX fifo size. All endpoints share the same FIFO area.
|
||||
let rx_fifo_size_words = RX_FIFO_EXTRA_SIZE_WORDS + ep_fifo_size(&self.ep_out);
|
||||
trace!("configuring rx fifo size={}", rx_fifo_size_words);
|
||||
|
||||
// SAFETY: register is exclusive to `Bus` with `&mut self`
|
||||
unsafe { r.grxfsiz().modify(|w| w.set_rxfd(rx_fifo_size_words)) };
|
||||
|
||||
// Configure TX (USB in direction) fifo size for each endpoint
|
||||
let mut fifo_top = rx_fifo_size_words;
|
||||
for i in 0..T::ENDPOINT_COUNT {
|
||||
if let Some(ep) = self.ep_in[i] {
|
||||
trace!(
|
||||
"configuring tx fifo ep={}, offset={}, size={}",
|
||||
i,
|
||||
fifo_top,
|
||||
ep.fifo_size_words
|
||||
);
|
||||
|
||||
let dieptxf = if i == 0 { r.dieptxf0() } else { r.dieptxf(i - 1) };
|
||||
|
||||
// SAFETY: register is exclusive to `Bus` with `&mut self`
|
||||
unsafe {
|
||||
dieptxf.write(|w| {
|
||||
w.set_fd(ep.fifo_size_words);
|
||||
w.set_sa(fifo_top);
|
||||
});
|
||||
}
|
||||
|
||||
fifo_top += ep.fifo_size_words;
|
||||
}
|
||||
}
|
||||
|
||||
assert!(
|
||||
fifo_top <= T::FIFO_DEPTH_WORDS,
|
||||
"FIFO allocations exceeded maximum capacity"
|
||||
);
|
||||
}
|
||||
|
||||
fn configure_endpoints(&mut self) {
|
||||
trace!("configure_endpoints");
|
||||
|
||||
let r = T::regs();
|
||||
|
||||
// Configure IN endpoints
|
||||
for (index, ep) in self.ep_in.iter().enumerate() {
|
||||
if let Some(ep) = ep {
|
||||
// SAFETY: DIEPCTL is shared with `Endpoint` so critical section is needed for RMW
|
||||
critical_section::with(|_| unsafe {
|
||||
r.diepctl(index).write(|w| {
|
||||
if index == 0 {
|
||||
w.set_mpsiz(ep0_mpsiz(ep.max_packet_size));
|
||||
} else {
|
||||
w.set_mpsiz(ep.max_packet_size);
|
||||
w.set_eptyp(to_eptyp(ep.ep_type));
|
||||
w.set_sd0pid_sevnfrm(true);
|
||||
}
|
||||
});
|
||||
});
|
||||
}
|
||||
}
|
||||
|
||||
// Configure OUT endpoints
|
||||
for (index, ep) in self.ep_out.iter().enumerate() {
|
||||
if let Some(ep) = ep {
|
||||
// SAFETY: DOEPCTL/DOEPTSIZ is shared with `Endpoint` so critical section is needed for RMW
|
||||
critical_section::with(|_| unsafe {
|
||||
r.doepctl(index).write(|w| {
|
||||
if index == 0 {
|
||||
w.set_mpsiz(ep0_mpsiz(ep.max_packet_size));
|
||||
} else {
|
||||
w.set_mpsiz(ep.max_packet_size);
|
||||
w.set_eptyp(to_eptyp(ep.ep_type));
|
||||
w.set_sd0pid_sevnfrm(true);
|
||||
}
|
||||
});
|
||||
|
||||
r.doeptsiz(index).modify(|w| {
|
||||
w.set_xfrsiz(ep.max_packet_size as _);
|
||||
if index == 0 {
|
||||
w.set_rxdpid_stupcnt(1);
|
||||
} else {
|
||||
w.set_pktcnt(1);
|
||||
}
|
||||
});
|
||||
});
|
||||
}
|
||||
}
|
||||
|
||||
// Enable IRQs for allocated endpoints
|
||||
// SAFETY: register is exclusive to `Bus` with `&mut self`
|
||||
unsafe {
|
||||
r.daintmsk().modify(|w| {
|
||||
w.set_iepm(ep_irq_mask(&self.ep_in));
|
||||
// OUT interrupts not used, handled in RXFLVL
|
||||
// w.set_oepm(ep_irq_mask(&self.ep_out));
|
||||
});
|
||||
}
|
||||
}
|
||||
|
||||
fn disable(&mut self) {
|
||||
unsafe { T::Interrupt::steal() }.disable();
|
||||
|
||||
<T as RccPeripheral>::disable();
|
||||
|
||||
#[cfg(stm32l4)]
|
||||
unsafe {
|
||||
crate::pac::PWR.cr2().modify(|w| w.set_usv(false));
|
||||
// Cannot disable PWR, because other peripherals might be using it
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl<'d, T: Instance> embassy_usb_driver::Bus for Bus<'d, T> {
|
||||
async fn poll(&mut self) -> Event {
|
||||
poll_fn(move |cx| {
|
||||
@ -902,9 +902,8 @@ impl<'d, T: Instance> embassy_usb_driver::Bus for Bus<'d, T> {
|
||||
<T as RccPeripheral>::enable();
|
||||
<T as RccPeripheral>::reset();
|
||||
|
||||
self.irq.set_handler(Self::on_interrupt);
|
||||
self.irq.unpend();
|
||||
self.irq.enable();
|
||||
T::Interrupt::steal().unpend();
|
||||
T::Interrupt::steal().enable();
|
||||
|
||||
let r = T::regs();
|
||||
let core_id = r.cid().read().0;
|
||||
|
Reference in New Issue
Block a user