stm32: move to bind_interrupts
disable lora functionality for now
This commit is contained in:
xoviat
@ -5,7 +5,7 @@ use core::marker::PhantomData;
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use core::sync::atomic::{compiler_fence, Ordering};
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use core::task::Poll;
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use embassy_cortex_m::interrupt::InterruptExt;
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use embassy_cortex_m::interrupt::{Interrupt, InterruptExt};
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use embassy_hal_common::drop::OnDrop;
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use embassy_hal_common::{into_ref, PeripheralRef};
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use futures::future::{select, Either};
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@ -18,7 +18,71 @@ use crate::pac::usart::Lpuart as Regs;
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use crate::pac::usart::Usart as Regs;
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use crate::pac::usart::{regs, vals};
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use crate::time::Hertz;
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use crate::{peripherals, Peripheral};
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use crate::{interrupt, peripherals, Peripheral};
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/// Interrupt handler.
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pub struct InterruptHandler<T: BasicInstance> {
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_phantom: PhantomData<T>,
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}
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impl<T: BasicInstance> interrupt::Handler<T::Interrupt> for InterruptHandler<T> {
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unsafe fn on_interrupt() {
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let r = T::regs();
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let s = T::state();
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let (sr, cr1, cr3) = unsafe { (sr(r).read(), r.cr1().read(), r.cr3().read()) };
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let mut wake = false;
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let has_errors = (sr.pe() && cr1.peie()) || ((sr.fe() || sr.ne() || sr.ore()) && cr3.eie());
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if has_errors {
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// clear all interrupts and DMA Rx Request
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unsafe {
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r.cr1().modify(|w| {
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// disable RXNE interrupt
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w.set_rxneie(false);
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// disable parity interrupt
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w.set_peie(false);
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// disable idle line interrupt
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w.set_idleie(false);
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});
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r.cr3().modify(|w| {
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// disable Error Interrupt: (Frame error, Noise error, Overrun error)
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w.set_eie(false);
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// disable DMA Rx Request
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w.set_dmar(false);
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});
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}
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wake = true;
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} else {
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if cr1.idleie() && sr.idle() {
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// IDLE detected: no more data will come
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unsafe {
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r.cr1().modify(|w| {
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// disable idle line detection
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w.set_idleie(false);
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});
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}
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wake = true;
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}
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if cr1.rxneie() {
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// We cannot check the RXNE flag as it is auto-cleared by the DMA controller
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// It is up to the listener to determine if this in fact was a RX event and disable the RXNE detection
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wake = true;
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}
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}
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if wake {
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compiler_fence(Ordering::SeqCst);
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s.rx_waker.wake();
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}
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}
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}
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#[derive(Clone, Copy, PartialEq, Eq, Debug)]
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pub enum DataBits {
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@ -215,7 +279,7 @@ impl<'d, T: BasicInstance, RxDma> UartRx<'d, T, RxDma> {
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/// Useful if you only want Uart Rx. It saves 1 pin and consumes a little less power.
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pub fn new(
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peri: impl Peripheral<P = T> + 'd,
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
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rx: impl Peripheral<P = impl RxPin<T>> + 'd,
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rx_dma: impl Peripheral<P = RxDma> + 'd,
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config: Config,
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@ -223,12 +287,12 @@ impl<'d, T: BasicInstance, RxDma> UartRx<'d, T, RxDma> {
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T::enable();
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T::reset();
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Self::new_inner(peri, irq, rx, rx_dma, config)
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Self::new_inner(peri, rx, rx_dma, config)
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}
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pub fn new_with_rts(
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peri: impl Peripheral<P = T> + 'd,
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
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rx: impl Peripheral<P = impl RxPin<T>> + 'd,
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rts: impl Peripheral<P = impl RtsPin<T>> + 'd,
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rx_dma: impl Peripheral<P = RxDma> + 'd,
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@ -246,17 +310,16 @@ impl<'d, T: BasicInstance, RxDma> UartRx<'d, T, RxDma> {
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});
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}
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Self::new_inner(peri, irq, rx, rx_dma, config)
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Self::new_inner(peri, rx, rx_dma, config)
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}
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fn new_inner(
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peri: impl Peripheral<P = T> + 'd,
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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rx: impl Peripheral<P = impl RxPin<T>> + 'd,
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rx_dma: impl Peripheral<P = RxDma> + 'd,
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config: Config,
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) -> Self {
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into_ref!(peri, irq, rx, rx_dma);
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into_ref!(peri, rx, rx_dma);
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let r = T::regs();
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@ -266,9 +329,8 @@ impl<'d, T: BasicInstance, RxDma> UartRx<'d, T, RxDma> {
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configure(r, &config, T::frequency(), T::KIND, true, false);
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irq.set_handler(Self::on_interrupt);
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irq.unpend();
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irq.enable();
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unsafe { T::Interrupt::steal() }.unpend();
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unsafe { T::Interrupt::steal() }.enable();
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// create state once!
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let _s = T::state();
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@ -282,63 +344,6 @@ impl<'d, T: BasicInstance, RxDma> UartRx<'d, T, RxDma> {
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}
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}
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fn on_interrupt(_: *mut ()) {
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let r = T::regs();
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let s = T::state();
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let (sr, cr1, cr3) = unsafe { (sr(r).read(), r.cr1().read(), r.cr3().read()) };
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let mut wake = false;
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let has_errors = (sr.pe() && cr1.peie()) || ((sr.fe() || sr.ne() || sr.ore()) && cr3.eie());
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if has_errors {
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// clear all interrupts and DMA Rx Request
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unsafe {
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r.cr1().modify(|w| {
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// disable RXNE interrupt
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w.set_rxneie(false);
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// disable parity interrupt
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w.set_peie(false);
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// disable idle line interrupt
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w.set_idleie(false);
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});
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r.cr3().modify(|w| {
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// disable Error Interrupt: (Frame error, Noise error, Overrun error)
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w.set_eie(false);
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// disable DMA Rx Request
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w.set_dmar(false);
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});
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}
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wake = true;
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} else {
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if cr1.idleie() && sr.idle() {
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// IDLE detected: no more data will come
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unsafe {
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r.cr1().modify(|w| {
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// disable idle line detection
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w.set_idleie(false);
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});
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}
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wake = true;
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}
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if cr1.rxneie() {
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// We cannot check the RXNE flag as it is auto-cleared by the DMA controller
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// It is up to the listener to determine if this in fact was a RX event and disable the RXNE detection
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wake = true;
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}
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}
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if wake {
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compiler_fence(Ordering::SeqCst);
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s.rx_waker.wake();
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}
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}
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#[cfg(any(usart_v1, usart_v2))]
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unsafe fn check_rx_flags(&mut self) -> Result<bool, Error> {
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let r = T::regs();
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@ -643,7 +648,7 @@ impl<'d, T: BasicInstance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
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peri: impl Peripheral<P = T> + 'd,
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rx: impl Peripheral<P = impl RxPin<T>> + 'd,
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tx: impl Peripheral<P = impl TxPin<T>> + 'd,
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
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tx_dma: impl Peripheral<P = TxDma> + 'd,
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rx_dma: impl Peripheral<P = RxDma> + 'd,
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config: Config,
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@ -651,14 +656,14 @@ impl<'d, T: BasicInstance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
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T::enable();
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T::reset();
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Self::new_inner(peri, rx, tx, irq, tx_dma, rx_dma, config)
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Self::new_inner(peri, rx, tx, tx_dma, rx_dma, config)
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}
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pub fn new_with_rtscts(
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peri: impl Peripheral<P = T> + 'd,
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rx: impl Peripheral<P = impl RxPin<T>> + 'd,
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tx: impl Peripheral<P = impl TxPin<T>> + 'd,
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
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rts: impl Peripheral<P = impl RtsPin<T>> + 'd,
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cts: impl Peripheral<P = impl CtsPin<T>> + 'd,
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tx_dma: impl Peripheral<P = TxDma> + 'd,
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@ -678,7 +683,7 @@ impl<'d, T: BasicInstance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
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w.set_ctse(true);
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});
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}
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Self::new_inner(peri, rx, tx, irq, tx_dma, rx_dma, config)
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Self::new_inner(peri, rx, tx, tx_dma, rx_dma, config)
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}
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#[cfg(not(any(usart_v1, usart_v2)))]
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@ -686,7 +691,7 @@ impl<'d, T: BasicInstance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
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peri: impl Peripheral<P = T> + 'd,
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rx: impl Peripheral<P = impl RxPin<T>> + 'd,
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tx: impl Peripheral<P = impl TxPin<T>> + 'd,
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
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de: impl Peripheral<P = impl DePin<T>> + 'd,
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tx_dma: impl Peripheral<P = TxDma> + 'd,
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rx_dma: impl Peripheral<P = RxDma> + 'd,
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@ -703,19 +708,18 @@ impl<'d, T: BasicInstance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
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w.set_dem(true);
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});
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}
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Self::new_inner(peri, rx, tx, irq, tx_dma, rx_dma, config)
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Self::new_inner(peri, rx, tx, tx_dma, rx_dma, config)
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}
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fn new_inner(
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peri: impl Peripheral<P = T> + 'd,
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rx: impl Peripheral<P = impl RxPin<T>> + 'd,
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tx: impl Peripheral<P = impl TxPin<T>> + 'd,
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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tx_dma: impl Peripheral<P = TxDma> + 'd,
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rx_dma: impl Peripheral<P = RxDma> + 'd,
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config: Config,
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) -> Self {
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into_ref!(peri, rx, tx, irq, tx_dma, rx_dma);
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into_ref!(peri, rx, tx, tx_dma, rx_dma);
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let r = T::regs();
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@ -726,9 +730,8 @@ impl<'d, T: BasicInstance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
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configure(r, &config, T::frequency(), T::KIND, true, true);
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irq.set_handler(UartRx::<T, RxDma>::on_interrupt);
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irq.unpend();
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irq.enable();
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unsafe { T::Interrupt::steal() }.unpend();
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unsafe { T::Interrupt::steal() }.enable();
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// create state once!
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let _s = T::state();
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@ -1068,6 +1071,9 @@ mod eio {
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#[cfg(feature = "nightly")]
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pub use buffered::*;
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#[cfg(feature = "nightly")]
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pub use crate::usart::buffered::InterruptHandler as BufferedInterruptHandler;
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#[cfg(feature = "nightly")]
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mod buffered;
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