Add bufferedUart, including a split version for only Rx or Tx
This commit is contained in:
Mathias
parent
9611e7c9f2
commit
31d85da78a
@ -9,31 +9,70 @@ use futures::future::poll_fn;
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use super::*;
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pub struct State<'d, T: Instance>(StateStorage<StateInner<'d, T>>);
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pub struct State<'d, T: Instance>(StateStorage<FullStateInner<'d, T>>);
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impl<'d, T: Instance> State<'d, T> {
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pub fn new() -> Self {
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pub const fn new() -> Self {
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Self(StateStorage::new())
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}
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}
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struct StateInner<'d, T: Instance> {
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phantom: PhantomData<&'d mut T>,
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rx_waker: WakerRegistration,
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rx: RingBuffer<'d>,
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tx_waker: WakerRegistration,
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tx: RingBuffer<'d>,
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pub struct RxState<'d, T: Instance>(StateStorage<RxStateInner<'d, T>>);
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impl<'d, T: Instance> RxState<'d, T> {
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pub const fn new() -> Self {
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Self(StateStorage::new())
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}
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}
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unsafe impl<'d, T: Instance> Send for StateInner<'d, T> {}
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unsafe impl<'d, T: Instance> Sync for StateInner<'d, T> {}
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pub struct TxState<'d, T: Instance>(StateStorage<TxStateInner<'d, T>>);
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impl<'d, T: Instance> TxState<'d, T> {
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pub const fn new() -> Self {
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Self(StateStorage::new())
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}
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}
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struct RxStateInner<'d, T: Instance> {
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phantom: PhantomData<&'d mut T>,
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waker: WakerRegistration,
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buf: RingBuffer<'d>,
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}
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struct TxStateInner<'d, T: Instance> {
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phantom: PhantomData<&'d mut T>,
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waker: WakerRegistration,
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buf: RingBuffer<'d>,
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}
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struct FullStateInner<'d, T: Instance> {
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rx: RxStateInner<'d, T>,
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tx: TxStateInner<'d, T>,
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}
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unsafe impl<'d, T: Instance> Send for RxStateInner<'d, T> {}
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unsafe impl<'d, T: Instance> Sync for RxStateInner<'d, T> {}
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unsafe impl<'d, T: Instance> Send for TxStateInner<'d, T> {}
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unsafe impl<'d, T: Instance> Sync for TxStateInner<'d, T> {}
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unsafe impl<'d, T: Instance> Send for FullStateInner<'d, T> {}
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unsafe impl<'d, T: Instance> Sync for FullStateInner<'d, T> {}
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pub struct BufferedUart<'d, T: Instance> {
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inner: PeripheralMutex<'d, StateInner<'d, T>>,
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inner: PeripheralMutex<'d, FullStateInner<'d, T>>,
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}
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pub struct RxBufferedUart<'d, T: Instance> {
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inner: PeripheralMutex<'d, RxStateInner<'d, T>>,
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}
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pub struct TxBufferedUart<'d, T: Instance> {
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inner: PeripheralMutex<'d, TxStateInner<'d, T>>,
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}
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impl<'d, T: Instance> Unpin for BufferedUart<'d, T> {}
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impl<'d, T: Instance> Unpin for RxBufferedUart<'d, T> {}
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impl<'d, T: Instance> Unpin for TxBufferedUart<'d, T> {}
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impl<'d, T: Instance> BufferedUart<'d, T> {
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pub fn new<M: Mode>(
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@ -55,66 +94,158 @@ impl<'d, T: Instance> BufferedUart<'d, T> {
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}
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Self {
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inner: PeripheralMutex::new(irq, &mut state.0, move || StateInner {
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phantom: PhantomData,
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tx: RingBuffer::new(tx_buffer),
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tx_waker: WakerRegistration::new(),
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rx: RingBuffer::new(rx_buffer),
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rx_waker: WakerRegistration::new(),
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inner: PeripheralMutex::new(irq, &mut state.0, move || FullStateInner {
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tx: TxStateInner {
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phantom: PhantomData,
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waker: WakerRegistration::new(),
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buf: RingBuffer::new(tx_buffer),
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},
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rx: RxStateInner {
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phantom: PhantomData,
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waker: WakerRegistration::new(),
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buf: RingBuffer::new(rx_buffer),
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},
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}),
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}
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}
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}
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impl<'d, T: Instance> StateInner<'d, T>
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impl<'d, T: Instance> RxBufferedUart<'d, T> {
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pub fn new<M: Mode>(
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state: &'d mut RxState<'d, T>,
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_uart: UartRx<'d, T, M>,
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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rx_buffer: &'d mut [u8],
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) -> RxBufferedUart<'d, T> {
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into_ref!(irq);
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let r = T::regs();
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unsafe {
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r.uartimsc().modify(|w| {
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// TODO: Should and more or fewer interrupts be enabled?
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w.set_rxim(true);
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w.set_rtim(true);
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});
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}
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Self {
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inner: PeripheralMutex::new(irq, &mut state.0, move || RxStateInner {
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phantom: PhantomData,
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buf: RingBuffer::new(rx_buffer),
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waker: WakerRegistration::new(),
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}),
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}
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}
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}
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impl<'d, T: Instance> TxBufferedUart<'d, T> {
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pub fn new<M: Mode>(
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state: &'d mut TxState<'d, T>,
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_uart: UartTx<'d, T, M>,
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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tx_buffer: &'d mut [u8],
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) -> TxBufferedUart<'d, T> {
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into_ref!(irq);
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let r = T::regs();
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unsafe {
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r.uartimsc().modify(|w| {
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// TODO: Should and more or fewer interrupts be enabled?
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w.set_rxim(true);
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w.set_rtim(true);
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});
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}
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Self {
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inner: PeripheralMutex::new(irq, &mut state.0, move || TxStateInner {
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phantom: PhantomData,
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buf: RingBuffer::new(tx_buffer),
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waker: WakerRegistration::new(),
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}),
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}
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}
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}
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impl<'d, T: Instance> PeripheralState for FullStateInner<'d, T>
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where
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Self: 'd,
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{
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fn on_rx(&mut self) {
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type Interrupt = T::Interrupt;
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fn on_interrupt(&mut self) {
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self.rx.on_interrupt();
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self.tx.on_interrupt();
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}
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}
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impl<'d, T: Instance> PeripheralState for RxStateInner<'d, T>
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where
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Self: 'd,
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{
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type Interrupt = T::Interrupt;
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fn on_interrupt(&mut self) {
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let r = T::regs();
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unsafe {
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let ris = r.uartris().read();
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let ris = r.uartmis().read();
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// Clear interrupt flags
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r.uarticr().write(|w| {
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r.uarticr().modify(|w| {
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w.set_rxic(true);
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w.set_rtic(true);
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});
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if ris.rxris() {
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if ris.peris() {
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if ris.rxmis() {
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if ris.pemis() {
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warn!("Parity error");
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r.uarticr().modify(|w| {
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w.set_peic(true);
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});
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}
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if ris.feris() {
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if ris.femis() {
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warn!("Framing error");
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r.uarticr().modify(|w| {
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w.set_feic(true);
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});
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}
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if ris.beris() {
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if ris.bemis() {
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warn!("Break error");
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r.uarticr().modify(|w| {
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w.set_beic(true);
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});
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}
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if ris.oeris() {
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if ris.oemis() {
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warn!("Overrun error");
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r.uarticr().modify(|w| {
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w.set_oeic(true);
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});
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}
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let buf = self.rx.push_buf();
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let buf = self.buf.push_buf();
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if !buf.is_empty() {
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buf[0] = r.uartdr().read().data();
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self.rx.push(1);
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self.buf.push(1);
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} else {
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warn!("RX buffer full, discard received byte");
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}
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if self.rx.is_full() {
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self.rx_waker.wake();
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if self.buf.is_full() {
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self.waker.wake();
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}
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}
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if ris.rtris() {
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self.rx_waker.wake();
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if ris.rtmis() {
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self.waker.wake();
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};
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}
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}
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}
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fn on_tx(&mut self) {
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impl<'d, T: Instance> PeripheralState for TxStateInner<'d, T>
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where
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Self: 'd,
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{
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type Interrupt = T::Interrupt;
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fn on_interrupt(&mut self) {
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let r = T::regs();
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unsafe {
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let ris = r.uartris().read();
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@ -124,14 +255,14 @@ where
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});
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if ris.txris() {
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let buf = self.tx.pop_buf();
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let buf = self.buf.pop_buf();
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if !buf.is_empty() {
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r.uartimsc().modify(|w| {
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w.set_txim(true);
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});
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r.uartdr().write(|w| w.set_data(buf[0].into()));
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self.tx.pop(1);
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self.tx_waker.wake();
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self.buf.pop(1);
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self.waker.wake();
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} else {
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// Disable interrupt until we have something to transmit again
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r.uartimsc().modify(|w| {
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@ -143,17 +274,6 @@ where
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}
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}
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impl<'d, T: Instance> PeripheralState for StateInner<'d, T>
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where
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Self: 'd,
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{
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type Interrupt = T::Interrupt;
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fn on_interrupt(&mut self) {
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self.on_rx();
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self.on_tx();
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}
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}
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impl embedded_io::Error for Error {
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fn kind(&self) -> embedded_io::ErrorKind {
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embedded_io::ErrorKind::Other
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@ -164,6 +284,14 @@ impl<'d, T: Instance> embedded_io::Io for BufferedUart<'d, T> {
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type Error = Error;
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}
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impl<'d, T: Instance> embedded_io::Io for RxBufferedUart<'d, T> {
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type Error = Error;
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}
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impl<'d, T: Instance> embedded_io::Io for TxBufferedUart<'d, T> {
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type Error = Error;
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}
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impl<'d, T: Instance + 'd> embedded_io::asynch::Read for BufferedUart<'d, T> {
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type ReadFuture<'a> = impl Future<Output = Result<usize, Self::Error>>
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where
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@ -176,20 +304,58 @@ impl<'d, T: Instance + 'd> embedded_io::asynch::Read for BufferedUart<'d, T> {
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compiler_fence(Ordering::SeqCst);
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// We have data ready in buffer? Return it.
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let data = state.rx.pop_buf();
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let data = state.rx.buf.pop_buf();
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if !data.is_empty() {
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let len = data.len().min(buf.len());
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buf[..len].copy_from_slice(&data[..len]);
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if state.rx.is_full() {
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if state.rx.buf.is_full() {
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do_pend = true;
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}
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state.rx.pop(len);
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state.rx.buf.pop(len);
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return Poll::Ready(Ok(len));
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}
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state.rx_waker.register(cx.waker());
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state.rx.waker.register(cx.waker());
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Poll::Pending
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});
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if do_pend {
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self.inner.pend();
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}
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res
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})
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}
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}
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impl<'d, T: Instance + 'd> embedded_io::asynch::Read for RxBufferedUart<'d, T> {
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type ReadFuture<'a> = impl Future<Output = Result<usize, Self::Error>>
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where
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Self: 'a;
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fn read<'a>(&'a mut self, buf: &'a mut [u8]) -> Self::ReadFuture<'a> {
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poll_fn(move |cx| {
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let mut do_pend = false;
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let res = self.inner.with(|state| {
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compiler_fence(Ordering::SeqCst);
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// We have data ready in buffer? Return it.
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let data = state.buf.pop_buf();
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if !data.is_empty() {
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let len = data.len().min(buf.len());
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buf[..len].copy_from_slice(&data[..len]);
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if state.buf.is_full() {
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do_pend = true;
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}
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state.buf.pop(len);
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return Poll::Ready(Ok(len));
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}
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state.waker.register(cx.waker());
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Poll::Pending
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});
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@ -213,7 +379,7 @@ impl<'d, T: Instance + 'd> embedded_io::asynch::BufRead for BufferedUart<'d, T>
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compiler_fence(Ordering::SeqCst);
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// We have data ready in buffer? Return it.
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let buf = state.rx.pop_buf();
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let buf = state.rx.buf.pop_buf();
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if !buf.is_empty() {
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let buf: &[u8] = buf;
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// Safety: buffer lives as long as uart
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@ -221,7 +387,7 @@ impl<'d, T: Instance + 'd> embedded_io::asynch::BufRead for BufferedUart<'d, T>
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return Poll::Ready(Ok(buf));
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}
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state.rx_waker.register(cx.waker());
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state.rx.waker.register(cx.waker());
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Poll::<Result<&[u8], Self::Error>>::Pending
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})
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})
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@ -229,8 +395,45 @@ impl<'d, T: Instance + 'd> embedded_io::asynch::BufRead for BufferedUart<'d, T>
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fn consume(&mut self, amt: usize) {
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let signal = self.inner.with(|state| {
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let full = state.rx.is_full();
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state.rx.pop(amt);
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let full = state.rx.buf.is_full();
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state.rx.buf.pop(amt);
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full
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});
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if signal {
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self.inner.pend();
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}
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}
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}
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impl<'d, T: Instance + 'd> embedded_io::asynch::BufRead for RxBufferedUart<'d, T> {
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type FillBufFuture<'a> = impl Future<Output = Result<&'a [u8], Self::Error>>
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where
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Self: 'a;
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fn fill_buf<'a>(&'a mut self) -> Self::FillBufFuture<'a> {
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poll_fn(move |cx| {
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self.inner.with(|state| {
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compiler_fence(Ordering::SeqCst);
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// We have data ready in buffer? Return it.
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let buf = state.buf.pop_buf();
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if !buf.is_empty() {
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let buf: &[u8] = buf;
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// Safety: buffer lives as long as uart
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let buf: &[u8] = unsafe { core::mem::transmute(buf) };
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return Poll::Ready(Ok(buf));
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}
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state.waker.register(cx.waker());
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Poll::<Result<&[u8], Self::Error>>::Pending
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})
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})
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}
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fn consume(&mut self, amt: usize) {
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let signal = self.inner.with(|state| {
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let full = state.buf.is_full();
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state.buf.pop(amt);
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full
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});
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if signal {
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@ -247,16 +450,16 @@ impl<'d, T: Instance + 'd> embedded_io::asynch::Write for BufferedUart<'d, T> {
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fn write<'a>(&'a mut self, buf: &'a [u8]) -> Self::WriteFuture<'a> {
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poll_fn(move |cx| {
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let (poll, empty) = self.inner.with(|state| {
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let empty = state.tx.is_empty();
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let tx_buf = state.tx.push_buf();
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let empty = state.tx.buf.is_empty();
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let tx_buf = state.tx.buf.push_buf();
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if tx_buf.is_empty() {
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state.tx_waker.register(cx.waker());
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state.tx.waker.register(cx.waker());
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return (Poll::Pending, empty);
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}
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let n = core::cmp::min(tx_buf.len(), buf.len());
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tx_buf[..n].copy_from_slice(&buf[..n]);
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state.tx.push(n);
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state.tx.buf.push(n);
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(Poll::Ready(Ok(n)), empty)
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});
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@ -274,8 +477,54 @@ impl<'d, T: Instance + 'd> embedded_io::asynch::Write for BufferedUart<'d, T> {
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fn flush<'a>(&'a mut self) -> Self::FlushFuture<'a> {
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poll_fn(move |cx| {
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self.inner.with(|state| {
|
||||
if !state.tx.is_empty() {
|
||||
state.tx_waker.register(cx.waker());
|
||||
if !state.tx.buf.is_empty() {
|
||||
state.tx.waker.register(cx.waker());
|
||||
return Poll::Pending;
|
||||
}
|
||||
|
||||
Poll::Ready(Ok(()))
|
||||
})
|
||||
})
|
||||
}
|
||||
}
|
||||
|
||||
impl<'d, T: Instance + 'd> embedded_io::asynch::Write for TxBufferedUart<'d, T> {
|
||||
type WriteFuture<'a> = impl Future<Output = Result<usize, Self::Error>>
|
||||
where
|
||||
Self: 'a;
|
||||
|
||||
fn write<'a>(&'a mut self, buf: &'a [u8]) -> Self::WriteFuture<'a> {
|
||||
poll_fn(move |cx| {
|
||||
let (poll, empty) = self.inner.with(|state| {
|
||||
let empty = state.buf.is_empty();
|
||||
let tx_buf = state.buf.push_buf();
|
||||
if tx_buf.is_empty() {
|
||||
state.waker.register(cx.waker());
|
||||
return (Poll::Pending, empty);
|
||||
}
|
||||
|
||||
let n = core::cmp::min(tx_buf.len(), buf.len());
|
||||
tx_buf[..n].copy_from_slice(&buf[..n]);
|
||||
state.buf.push(n);
|
||||
|
||||
(Poll::Ready(Ok(n)), empty)
|
||||
});
|
||||
if empty {
|
||||
self.inner.pend();
|
||||
}
|
||||
poll
|
||||
})
|
||||
}
|
||||
|
||||
type FlushFuture<'a> = impl Future<Output = Result<(), Self::Error>>
|
||||
where
|
||||
Self: 'a;
|
||||
|
||||
fn flush<'a>(&'a mut self) -> Self::FlushFuture<'a> {
|
||||
poll_fn(move |cx| {
|
||||
self.inner.with(|state| {
|
||||
if !state.buf.is_empty() {
|
||||
state.waker.register(cx.waker());
|
||||
return Poll::Pending;
|
||||
}
|
||||
|
||||
|
||||
@ -343,7 +343,7 @@ impl<'d, T: Instance, M: Mode> Uart<'d, T, M> {
|
||||
w.set_stp2(config.stop_bits == StopBits::STOP2);
|
||||
w.set_pen(pen);
|
||||
w.set_eps(eps);
|
||||
w.set_fen(true);
|
||||
w.set_fen(false);
|
||||
});
|
||||
|
||||
r.uartcr().write(|w| {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user