STM32 DAC: Swap to new TSEL enum entirely in-HAL
This commit is contained in:
Adam Greig
Dario Nieuwenhuis
parent
135f350020
commit
31fc337e2f
@ -10,6 +10,9 @@ use crate::pac::dac;
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use crate::rcc::RccPeripheral;
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use crate::{peripherals, Peripheral};
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mod tsel;
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pub use tsel::TriggerSel;
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#[cfg(any(dac_v3, dac_v4, dac_v5, dac_v6, dac_v7))]
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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@ -51,7 +54,6 @@ impl Mode {
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}
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}
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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/// Custom Errors
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@ -77,100 +79,6 @@ impl Channel {
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}
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}
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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/// Trigger sources for CH1
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pub enum Ch1Trigger {
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#[cfg(dac_v3)]
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Tim1,
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Tim2,
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#[cfg(not(dac_v3))]
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Tim3,
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#[cfg(dac_v3)]
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Tim4,
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#[cfg(dac_v3)]
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Tim5,
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Tim6,
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Tim7,
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#[cfg(dac_v3)]
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Tim8,
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Tim15,
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#[cfg(dac_v3)]
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Hrtim1Dactrg1,
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#[cfg(dac_v3)]
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Hrtim1Dactrg2,
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#[cfg(dac_v3)]
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Lptim1,
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#[cfg(dac_v3)]
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Lptim2,
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#[cfg(dac_v3)]
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Lptim3,
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Exti9,
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Software,
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}
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impl Ch1Trigger {
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fn tsel(&self) -> dac::vals::Tsel1 {
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match self {
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#[cfg(dac_v3)]
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Ch1Trigger::Tim1 => dac::vals::Tsel1::TIM1_TRGO,
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Ch1Trigger::Tim2 => dac::vals::Tsel1::TIM2_TRGO,
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#[cfg(not(dac_v3))]
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Ch1Trigger::Tim3 => dac::vals::Tsel1::TIM3_TRGO,
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#[cfg(dac_v3)]
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Ch1Trigger::Tim4 => dac::vals::Tsel1::TIM4_TRGO,
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#[cfg(dac_v3)]
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Ch1Trigger::Tim5 => dac::vals::Tsel1::TIM5_TRGO,
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Ch1Trigger::Tim6 => dac::vals::Tsel1::TIM6_TRGO,
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Ch1Trigger::Tim7 => dac::vals::Tsel1::TIM7_TRGO,
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#[cfg(dac_v3)]
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Ch1Trigger::Tim8 => dac::vals::Tsel1::TIM8_TRGO,
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Ch1Trigger::Tim15 => dac::vals::Tsel1::TIM15_TRGO,
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#[cfg(dac_v3)]
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Ch1Trigger::Hrtim1Dactrg1 => dac::vals::Tsel1::HRTIM1_DACTRG1,
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#[cfg(dac_v3)]
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Ch1Trigger::Hrtim1Dactrg2 => dac::vals::Tsel1::HRTIM1_DACTRG2,
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#[cfg(dac_v3)]
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Ch1Trigger::Lptim1 => dac::vals::Tsel1::LPTIM1_OUT,
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#[cfg(dac_v3)]
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Ch1Trigger::Lptim2 => dac::vals::Tsel1::LPTIM2_OUT,
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#[cfg(dac_v3)]
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Ch1Trigger::Lptim3 => dac::vals::Tsel1::LPTIM3_OUT,
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Ch1Trigger::Exti9 => dac::vals::Tsel1::EXTI9,
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Ch1Trigger::Software => dac::vals::Tsel1::SOFTWARE,
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}
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}
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}
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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/// Trigger sources for CH2
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pub enum Ch2Trigger {
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Tim6,
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Tim8,
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Tim7,
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Tim5,
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Tim2,
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Tim4,
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Exti9,
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Software,
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}
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impl Ch2Trigger {
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fn tsel(&self) -> dac::vals::Tsel2 {
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match self {
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Ch2Trigger::Tim6 => dac::vals::Tsel2::TIM6_TRGO,
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Ch2Trigger::Tim8 => dac::vals::Tsel2::TIM8_TRGO,
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Ch2Trigger::Tim7 => dac::vals::Tsel2::TIM7_TRGO,
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Ch2Trigger::Tim5 => dac::vals::Tsel2::TIM5_TRGO,
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Ch2Trigger::Tim2 => dac::vals::Tsel2::TIM2_TRGO,
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Ch2Trigger::Tim4 => dac::vals::Tsel2::TIM4_TRGO,
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Ch2Trigger::Exti9 => dac::vals::Tsel2::EXTI9,
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Ch2Trigger::Software => dac::vals::Tsel2::SOFTWARE,
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}
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}
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}
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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/// Single 8 or 12 bit value that can be output by the DAC
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@ -315,10 +223,10 @@ impl<'d, T: Instance, Tx> DacCh1<'d, T, Tx> {
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/// Select a new trigger for this channel
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///
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/// **Important**: This disables the channel!
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pub fn select_trigger(&mut self, trigger: Ch1Trigger) -> Result<(), Error> {
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pub fn select_trigger(&mut self, trigger: TriggerSel) -> Result<(), Error> {
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unwrap!(self.disable_channel());
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T::regs().cr().modify(|reg| {
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reg.set_tsel1(trigger.tsel());
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reg.set_tsel(0, trigger.tsel());
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});
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Ok(())
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}
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@ -426,10 +334,10 @@ impl<'d, T: Instance, Tx> DacCh2<'d, T, Tx> {
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}
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/// Select a new trigger for this channel
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pub fn select_trigger(&mut self, trigger: Ch2Trigger) -> Result<(), Error> {
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pub fn select_trigger(&mut self, trigger: TriggerSel) -> Result<(), Error> {
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unwrap!(self.disable_channel());
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T::regs().cr().modify(|reg| {
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reg.set_tsel2(trigger.tsel());
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reg.set_tsel(1, trigger.tsel());
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});
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Ok(())
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}
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282
embassy-stm32/src/dac/tsel.rs
Normal file
282
embassy-stm32/src/dac/tsel.rs
Normal file
@ -0,0 +1,282 @@
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/// Trigger selection for STM32F0.
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#[cfg(stm32f0)]
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum TriggerSel {
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Tim6 = 0,
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Tim3 = 1,
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Tim7 = 2,
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Tim15 = 3,
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Tim2 = 4,
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Exti9 = 6,
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Software = 7,
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}
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/// Trigger selection for STM32F1.
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#[cfg(stm32f1)]
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum TriggerSel {
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Tim6 = 0,
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#[cfg(any(stm32f100, stm32f105, stm32f107))]
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Tim3 = 1,
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#[cfg(any(stm32f101, stm32f103))]
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Tim8 = 1,
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Tim7 = 2,
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#[cfg(any(stm32f101, stm32f103, stm32f105, stm32f107))]
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Tim5 = 3,
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#[cfg(all(stm32f100, any(flashsize_4, flashsize_6, flashsize_8, flashsize_b)))]
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Tim15 = 3,
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#[cfg(all(stm32f100, any(flashsize_c, flashsize_d, flashsize_e)))]
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/// Can be remapped to TIM15 with MISC_REMAP in AFIO_MAPR2.
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Tim5Or15 = 3,
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Tim2 = 4,
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Tim4 = 5,
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Exti9 = 6,
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Software = 7,
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}
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/// Trigger selection for STM32F2/F4/F7/L4, except F410 or L4+.
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#[cfg(all(any(stm32f2, stm32f4, stm32f7, stm32l4_nonplus), not(stm32f410)))]
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum TriggerSel {
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Tim6 = 0,
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Tim8 = 1,
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#[cfg(not(any(stm32l45x, stm32l46x)))]
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Tim7 = 2,
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Tim5 = 3,
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Tim2 = 4,
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Tim4 = 5,
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Exti9 = 6,
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Software = 7,
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}
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/// Trigger selection for STM32F410.
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#[cfg(stm32f410)]
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum TriggerSel {
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Tim5 = 3,
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Exti9 = 6,
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Software = 7,
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}
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/// Trigger selection for STM32F301/2 and 318.
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#[cfg(any(stm32f301, stm32f302, stm32f318))]
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum TriggerSel {
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Tim6 = 0,
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#[cfg(stm32f302)]
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/// Requires DAC_TRIG_RMP set in SYSCFG_CFGR1.
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Tim3 = 1,
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Tim15 = 3,
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Tim2 = 4,
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#[cfg(all(stm32f302, any(flashsize_6, flashsize_8)))]
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Tim4 = 5,
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Exti9 = 6,
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Software = 7,
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}
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/// Trigger selection for STM32F303/3x8 (excluding 318 which is like 301, and 378 which is 37x).
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#[cfg(any(stm32f303, stm32f328, stm32f358, stm32f398))]
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum TriggerSel {
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Tim6 = 0,
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/// * DAC1: defaults to TIM8 but can be remapped to TIM3 with DAC_TRIG_RMP in SYSCFG_CFGR1
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/// * DAC2: always TIM3
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Tim8Or3 = 1,
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Tim7 = 2,
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Tim15 = 3,
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Tim2 = 4,
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Tim4 = 5,
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Exti9 = 6,
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Software = 7,
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}
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/// Trigger selection for STM32F37x.
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#[cfg(any(stm32f373, stm32f378))]
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum TriggerSel {
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Tim6 = 0,
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Tim3 = 1,
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Tim7 = 2,
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/// TIM5 on DAC1, TIM18 on DAC2
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Dac1Tim5Dac2Tim18 = 3,
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Tim2 = 4,
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Tim4 = 5,
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Exti9 = 6,
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Software = 7,
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}
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/// Trigger selection for STM32F334.
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#[cfg(stm32f334)]
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum TriggerSel {
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Tim6 = 0,
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/// Requires DAC_TRIG_RMP set in SYSCFG_CFGR1.
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Tim3 = 1,
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Tim7 = 2,
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/// Can be remapped to HRTIM_DACTRG1 using DAC1_TRIG3_RMP in SYSCFG_CFGR3.
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Tim15OrHrtimDacTrg1 = 3,
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Tim2 = 4,
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/// Requires DAC_TRIG5_RMP set in SYSCFG_CFGR3.
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HrtimDacTrg2 = 5,
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}
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/// Trigger selection for STM32L0.
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#[cfg(stm32l0)]
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum TriggerSel {
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Tim6 = 0,
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Tim3 = 1,
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Tim3Ch3 = 2,
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Tim21 = 3,
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Tim2 = 4,
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Tim7 = 5,
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Exti9 = 6,
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Software = 7,
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}
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/// Trigger selection for STM32L1.
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#[cfg(stm32l1)]
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum TriggerSel {
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Tim6 = 0,
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Tim7 = 2,
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Tim9 = 3,
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Tim2 = 4,
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Tim4 = 5,
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Exti9 = 6,
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Software = 7,
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}
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/// Trigger selection for L4+, L5, U5, H7.
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#[cfg(any(stm32l4_plus, stm32l5, stm32u5, stm32h7))]
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum TriggerSel {
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Software = 0,
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Tim1 = 1,
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Tim2 = 2,
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Tim4 = 3,
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Tim5 = 4,
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Tim6 = 5,
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Tim7 = 6,
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Tim8 = 7,
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Tim15 = 8,
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#[cfg(all(stm32h7, hrtim))]
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Hrtim1DacTrg1 = 9,
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#[cfg(all(stm32h7, hrtim))]
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Hrtim1DacTrg2 = 10,
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Lptim1 = 11,
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#[cfg(not(stm32u5))]
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Lptim2 = 12,
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#[cfg(stm32u5)]
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Lptim3 = 12,
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Exti9 = 13,
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#[cfg(any(stm32h7ax, stm32h7bx))]
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/// RM0455 suggests this might be LPTIM2 on DAC1 and LPTIM3 on DAC2,
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/// but it's probably wrong. Please let us know if you find out.
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Lptim3 = 14,
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#[cfg(any(stm32h72x, stm32h73x))]
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Tim23 = 14,
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#[cfg(any(stm32h72x, stm32h73x))]
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Tim24 = 15,
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}
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/// Trigger selection for H5.
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#[cfg(stm32h5)]
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum TriggerSel {
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Software = 0,
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Tim1 = 1,
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Tim2 = 2,
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#[cfg(any(stm32h56x, stm32h57x))]
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Tim4 = 3,
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#[cfg(stm32h503)]
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Tim3 = 3,
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#[cfg(any(stm32h56x, stm32h57x))]
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Tim5 = 4,
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Tim6 = 5,
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Tim7 = 6,
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#[cfg(any(stm32h56x, stm32h57x))]
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Tim8 = 7,
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#[cfg(any(stm32h56x, stm32h57x))]
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Tim15 = 8,
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Lptim1 = 11,
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Lptim2 = 12,
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Exti9 = 13,
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}
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/// Trigger selection for G0.
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#[cfg(stm32g0)]
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum TriggerSel {
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Software = 0,
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Tim1 = 1,
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Tim2 = 2,
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Tim3 = 3,
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Tim6 = 5,
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Tim7 = 6,
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Tim15 = 8,
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Lptim1 = 11,
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Lptim2 = 12,
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Exti9 = 13,
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}
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/// Trigger selection for G4.
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#[cfg(stm32g4)]
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum TriggerSel {
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Software = 0,
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/// * DAC1, DAC2, DAC4: TIM8
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/// * DAC3: TIM1
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Dac124Tim8Dac3Tim1 = 1,
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Tim7 = 2,
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Tim15 = 3,
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Tim2 = 4,
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Tim4 = 5,
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Exti9 = 6,
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Tim6 = 7,
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Tim3 = 8,
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HrtimDacRstTrg1 = 9,
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HrtimDacRstTrg2 = 10,
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HrtimDacRstTrg3 = 11,
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HrtimDacRstTrg4 = 12,
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HrtimDacRstTrg5 = 13,
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HrtimDacRstTrg6 = 14,
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/// * DAC1, DAC4: HRTIM_DAC_TRG1
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/// * DAC2: HRTIM_DAC_TRG2
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/// * DAC3: HRTIM_DAC_TRG3
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HrtimDacTrg123 = 15,
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}
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/// Trigger selection for WL.
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#[cfg(stm32wl)]
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum TriggerSel {
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Software = 0,
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Tim1 = 1,
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Tim2 = 2,
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Lptim1 = 11,
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Lptim2 = 12,
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Lptim3 = 13,
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Exti9 = 14,
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}
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impl TriggerSel {
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pub fn tsel(&self) -> u8 {
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*self as u8
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}
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}
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@ -77,7 +77,7 @@ async fn dac_task1(mut dac: Dac1Type) {
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error!("Reload value {} below threshold!", reload);
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}
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dac.select_trigger(embassy_stm32::dac::Ch1Trigger::Tim6).unwrap();
|
||||
dac.select_trigger(embassy_stm32::dac::TriggerSel::Tim6).unwrap();
|
||||
dac.enable_channel().unwrap();
|
||||
|
||||
TIM6::enable_and_reset();
|
||||
@ -127,7 +127,7 @@ async fn dac_task2(mut dac: Dac2Type) {
|
||||
w.set_cen(true);
|
||||
});
|
||||
|
||||
dac.select_trigger(embassy_stm32::dac::Ch2Trigger::Tim7).unwrap();
|
||||
dac.select_trigger(embassy_stm32::dac::TriggerSel::Tim7).unwrap();
|
||||
|
||||
debug!(
|
||||
"TIM7 Frequency {}, Target Frequency {}, Reload {}, Reload as u16 {}, Samples {}",
|
||||
|
||||
@ -48,7 +48,7 @@ async fn dac_task1(mut dac: Dac1Type) {
|
||||
error!("Reload value {} below threshold!", reload);
|
||||
}
|
||||
|
||||
dac.select_trigger(embassy_stm32::dac::Ch1Trigger::Tim6).unwrap();
|
||||
dac.select_trigger(embassy_stm32::dac::TriggerSel::Tim6).unwrap();
|
||||
dac.enable_channel().unwrap();
|
||||
|
||||
TIM6::enable_and_reset();
|
||||
@ -98,7 +98,7 @@ async fn dac_task2(mut dac: Dac2Type) {
|
||||
w.set_cen(true);
|
||||
});
|
||||
|
||||
dac.select_trigger(embassy_stm32::dac::Ch2Trigger::Tim7).unwrap();
|
||||
dac.select_trigger(embassy_stm32::dac::TriggerSel::Tim7).unwrap();
|
||||
|
||||
debug!(
|
||||
"TIM7 Frequency {}, Target Frequency {}, Reload {}, Reload as u16 {}, Samples {}",
|
||||
|
||||
Loading…
Reference in New Issue
Block a user