max/embassy
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Merge branch 'master' of https://github.com/akiles/embassy into st-usb

Browse Source
This commit is contained in:
xoviat
2021-03-27 21:24:21 -05:00
parent d4f35c1729 19b959b0f8
commit 3242990690
25 changed files with 638 additions and 349 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
embassy-stm32f4/Cargo.toml
View File

@ -37,6 +37,7 @@ defmt = { version = "0.2.0", optional = true }
log = { version = "0.4.11", optional = true }
cortex-m-rt = "0.6.13"
cortex-m = "0.7.1"
futures = { version = "0.3.5", default-features = false, features = ["async-await"] }
embedded-hal = { version = "0.2.4" }
embedded-dma = { version = "0.1.2" }
stm32f4xx-hal = { version = "0.8.3", features = ["rt", "can"], git = "https://github.com/stm32-rs/stm32f4xx-hal.git"}

101
embassy-stm32f4/src/can.rs
View File

@ -1,101 +0,0 @@
//! Async low power Serial.
//!
//! The peripheral is autmatically enabled and disabled as required to save power.
//! Lowest power consumption can only be guaranteed if the send receive futures
//! are dropped correctly (e.g. not using `mem::forget()`).
use bxcan;
use bxcan::Interrupts;
use core::future::Future;
use embassy::interrupt::Interrupt;
use embassy::util::InterruptFuture;
use nb;
use nb::block;
use crate::interrupt;
/// Interface to the Serial peripheral
pub struct Can<T: Instance> {
can: bxcan::Can<T>,
tx_int: T::TInterrupt,
rx_int: T::RInterrupt,
}
impl<T: Instance> Can<T> {
pub fn new(mut can: bxcan::Can<T>, tx_int: T::TInterrupt, rx_int: T::RInterrupt) -> Self {
// Sync to the bus and start normal operation.
can.enable_interrupts(
Interrupts::TRANSMIT_MAILBOX_EMPTY | Interrupts::FIFO0_MESSAGE_PENDING,
);
block!(can.enable()).unwrap();
Can {
can: can,
tx_int: tx_int,
rx_int: rx_int,
}
}
/// Sends can frame.
///
/// This method async-blocks until the frame is transmitted.
pub fn transmit<'a>(&'a mut self, frame: &'a bxcan::Frame) -> impl Future<Output = ()> + 'a {
async move {
let fut = InterruptFuture::new(&mut self.tx_int);
// Infallible
self.can.transmit(frame).unwrap();
fut.await;
}
}
/// Receive can frame.
///
/// This method async-blocks until the frame is received.
pub fn receive<'a>(&'a mut self) -> impl Future<Output = bxcan::Frame> + 'a {
async move {
let mut frame: Option<bxcan::Frame>;
loop {
let fut = InterruptFuture::new(&mut self.rx_int);
frame = match self.can.receive() {
Ok(frame) => Some(frame),
Err(nb::Error::WouldBlock) => None,
Err(nb::Error::Other(_)) => None, // Ignore overrun errors.
};
if frame.is_some() {
break;
}
fut.await;
}
frame.unwrap()
}
}
}
mod private {
pub trait Sealed {}
}
pub trait Instance: bxcan::Instance + private::Sealed {
type TInterrupt: Interrupt;
type RInterrupt: Interrupt;
}
macro_rules! can {
($($can:ident => ($tint:ident, $rint:ident),)+) => {
$(
impl private::Sealed for crate::hal::can::Can<crate::pac::$can> {}
impl Instance for crate::hal::can::Can<crate::pac::$can> {
type TInterrupt = interrupt::$tint;
type RInterrupt = interrupt::$rint;
}
)+
}
}
can! {
CAN1 => (CAN1_TX, CAN1_RX0),
CAN2 => (CAN2_TX, CAN2_RX0),
}

535
embassy-stm32f4/src/exti.rs
View File

@ -1,535 +0,0 @@
use core::future::Future;
use core::mem;
use core::pin::Pin;
use cortex_m;
use embassy::traits::gpio::{WaitForFallingEdge, WaitForRisingEdge};
use embassy::util::InterruptFuture;
use crate::hal::gpio;
use crate::hal::gpio::Edge;
use crate::hal::syscfg::SysCfg;
use crate::pac::EXTI;
use embedded_hal::digital::v2 as digital;
use crate::interrupt;
pub struct ExtiPin<T: gpio::ExtiPin + WithInterrupt> {
pin: T,
interrupt: T::Interrupt,
}
impl<T: gpio::ExtiPin + WithInterrupt> ExtiPin<T> {
pub fn new(mut pin: T, interrupt: T::Interrupt) -> Self {
let mut syscfg: SysCfg = unsafe { mem::transmute(()) };
cortex_m::interrupt::free(|_| {
pin.make_interrupt_source(&mut syscfg);
});
Self { pin, interrupt }
}
}
impl<T: gpio::ExtiPin + WithInterrupt + digital::OutputPin> digital::OutputPin for ExtiPin<T> {
type Error = T::Error;
fn set_low(&mut self) -> Result<(), Self::Error> {
self.pin.set_low()
}
fn set_high(&mut self) -> Result<(), Self::Error> {
self.pin.set_high()
}
}
impl<T: gpio::ExtiPin + WithInterrupt + digital::StatefulOutputPin> digital::StatefulOutputPin
for ExtiPin<T>
{
fn is_set_low(&self) -> Result<bool, Self::Error> {
self.pin.is_set_low()
}
fn is_set_high(&self) -> Result<bool, Self::Error> {
self.pin.is_set_high()
}
}
impl<T: gpio::ExtiPin + WithInterrupt + digital::ToggleableOutputPin> digital::ToggleableOutputPin
for ExtiPin<T>
{
type Error = T::Error;
fn toggle(&mut self) -> Result<(), Self::Error> {
self.pin.toggle()
}
}
impl<T: gpio::ExtiPin + WithInterrupt + digital::InputPin> digital::InputPin for ExtiPin<T> {
type Error = T::Error;
fn is_high(&self) -> Result<bool, Self::Error> {
self.pin.is_high()
}
fn is_low(&self) -> Result<bool, Self::Error> {
self.pin.is_low()
}
}
/*
Irq Handler Description
EXTI0_IRQn EXTI0_IRQHandler Handler for pins connected to line 0
EXTI1_IRQn EXTI1_IRQHandler Handler for pins connected to line 1
EXTI2_IRQn EXTI2_IRQHandler Handler for pins connected to line 2
EXTI3_IRQn EXTI3_IRQHandler Handler for pins connected to line 3
EXTI4_IRQn EXTI4_IRQHandler Handler for pins connected to line 4
EXTI9_5_IRQn EXTI9_5_IRQHandler Handler for pins connected to line 5 to 9
EXTI15_10_IRQn EXTI15_10_IRQHandler Handler for pins connected to line 10 to 15
*/
impl<T: gpio::ExtiPin + WithInterrupt + 'static> WaitForRisingEdge for ExtiPin<T> {
type Future<'a> = impl Future<Output = ()> + 'a;
fn wait_for_rising_edge<'a>(self: Pin<&'a mut Self>) -> Self::Future<'a> {
let s = unsafe { self.get_unchecked_mut() };
s.pin.clear_interrupt_pending_bit();
async move {
let fut = InterruptFuture::new(&mut s.interrupt);
let pin = &mut s.pin;
cortex_m::interrupt::free(|_| {
let mut exti: EXTI = unsafe { mem::transmute(()) };
pin.trigger_on_edge(&mut exti, Edge::RISING);
pin.enable_interrupt(&mut exti);
});
fut.await;
s.pin.clear_interrupt_pending_bit();
}
}
}
impl<T: gpio::ExtiPin + WithInterrupt + 'static> WaitForFallingEdge for ExtiPin<T> {
type Future<'a> = impl Future<Output = ()> + 'a;
fn wait_for_falling_edge<'a>(self: Pin<&'a mut Self>) -> Self::Future<'a> {
let s = unsafe { self.get_unchecked_mut() };
s.pin.clear_interrupt_pending_bit();
async move {
let fut = InterruptFuture::new(&mut s.interrupt);
let pin = &mut s.pin;
cortex_m::interrupt::free(|_| {
let mut exti: EXTI = unsafe { mem::transmute(()) };
pin.trigger_on_edge(&mut exti, Edge::FALLING);
pin.enable_interrupt(&mut exti);
});
fut.await;
s.pin.clear_interrupt_pending_bit();
}
}
}
mod private {
pub trait Sealed {}
}
pub trait WithInterrupt: private::Sealed {
type Interrupt: interrupt::Interrupt;
}
macro_rules! exti {
($set:ident, [
$($INT:ident => $pin:ident,)+
]) => {
$(
impl<T> private::Sealed for gpio::$set::$pin<T> {}
impl<T> WithInterrupt for gpio::$set::$pin<T> {
type Interrupt = interrupt::$INT;
}
)+
};
}
#[cfg(any(
feature = "stm32f401",
feature = "stm32f405",
feature = "stm32f407",
feature = "stm32f410",
feature = "stm32f411",
feature = "stm32f412",
feature = "stm32f413",
feature = "stm32f415",
feature = "stm32f417",
feature = "stm32f423",
feature = "stm32f427",
feature = "stm32f429",
feature = "stm32f437",
feature = "stm32f439",
feature = "stm32f446",
feature = "stm32f469",
feature = "stm32f479"
))]
exti!(gpioa, [
EXTI0 => PA0,
EXTI1 => PA1,
EXTI2 => PA2,
EXTI3 => PA3,
EXTI4 => PA4,
EXTI9_5 => PA5,
EXTI9_5 => PA6,
EXTI9_5 => PA7,
EXTI9_5 => PA8,
EXTI9_5 => PA9,
EXTI15_10 => PA10,
EXTI15_10 => PA11,
EXTI15_10 => PA12,
EXTI15_10 => PA13,
EXTI15_10 => PA14,
EXTI15_10 => PA15,
]);
#[cfg(any(
feature = "stm32f401",
feature = "stm32f405",
feature = "stm32f407",
feature = "stm32f410",
feature = "stm32f411",
feature = "stm32f412",
feature = "stm32f413",
feature = "stm32f415",
feature = "stm32f417",
feature = "stm32f423",
feature = "stm32f427",
feature = "stm32f429",
feature = "stm32f437",
feature = "stm32f439",
feature = "stm32f446",
feature = "stm32f469",
feature = "stm32f479"
))]
exti!(gpiob, [
EXTI0 => PB0,
EXTI1 => PB1,
EXTI2 => PB2,
EXTI3 => PB3,
EXTI4 => PB4,
EXTI9_5 => PB5,
EXTI9_5 => PB6,
EXTI9_5 => PB7,
EXTI9_5 => PB8,
EXTI9_5 => PB9,
EXTI15_10 => PB10,
EXTI15_10 => PB11,
EXTI15_10 => PB12,
EXTI15_10 => PB13,
EXTI15_10 => PB14,
EXTI15_10 => PB15,
]);
#[cfg(any(
feature = "stm32f401",
feature = "stm32f405",
feature = "stm32f407",
feature = "stm32f410",
feature = "stm32f411",
feature = "stm32f412",
feature = "stm32f413",
feature = "stm32f415",
feature = "stm32f417",
feature = "stm32f423",
feature = "stm32f427",
feature = "stm32f429",
feature = "stm32f437",
feature = "stm32f439",
feature = "stm32f446",
feature = "stm32f469",
feature = "stm32f479"
))]
exti!(gpioc, [
EXTI0 => PC0,
EXTI1 => PC1,
EXTI2 => PC2,
EXTI3 => PC3,
EXTI4 => PC4,
EXTI9_5 => PC5,
EXTI9_5 => PC6,
EXTI9_5 => PC7,
EXTI9_5 => PC8,
EXTI9_5 => PC9,
EXTI15_10 => PC10,
EXTI15_10 => PC11,
EXTI15_10 => PC12,
EXTI15_10 => PC13,
EXTI15_10 => PC14,
EXTI15_10 => PC15,
]);
#[cfg(any(
feature = "stm32f401",
feature = "stm32f405",
feature = "stm32f407",
feature = "stm32f411",
feature = "stm32f412",
feature = "stm32f413",
feature = "stm32f415",
feature = "stm32f417",
feature = "stm32f423",
feature = "stm32f427",
feature = "stm32f429",
feature = "stm32f437",
feature = "stm32f439",
feature = "stm32f446",
feature = "stm32f469",
feature = "stm32f479"
))]
exti!(gpiod, [
EXTI0 => PD0,
EXTI1 => PD1,
EXTI2 => PD2,
EXTI3 => PD3,
EXTI4 => PD4,
EXTI9_5 => PD5,
EXTI9_5 => PD6,
EXTI9_5 => PD7,
EXTI9_5 => PD8,
EXTI9_5 => PD9,
EXTI15_10 => PD10,
EXTI15_10 => PD11,
EXTI15_10 => PD12,
EXTI15_10 => PD13,
EXTI15_10 => PD14,
EXTI15_10 => PD15,
]);
#[cfg(any(
feature = "stm32f401",
feature = "stm32f405",
feature = "stm32f407",
feature = "stm32f411",
feature = "stm32f412",
feature = "stm32f413",
feature = "stm32f415",
feature = "stm32f417",
feature = "stm32f423",
feature = "stm32f427",
feature = "stm32f429",
feature = "stm32f437",
feature = "stm32f439",
feature = "stm32f446",
feature = "stm32f469",
feature = "stm32f479"
))]
exti!(gpioe, [
EXTI0 => PE0,
EXTI1 => PE1,
EXTI2 => PE2,
EXTI3 => PE3,
EXTI4 => PE4,
EXTI9_5 => PE5,
EXTI9_5 => PE6,
EXTI9_5 => PE7,
EXTI9_5 => PE8,
EXTI9_5 => PE9,
EXTI15_10 => PE10,
EXTI15_10 => PE11,
EXTI15_10 => PE12,
EXTI15_10 => PE13,
EXTI15_10 => PE14,
EXTI15_10 => PE15,
]);
#[cfg(any(
feature = "stm32f405",
feature = "stm32f407",
feature = "stm32f412",
feature = "stm32f413",
feature = "stm32f415",
feature = "stm32f417",
feature = "stm32f423",
feature = "stm32f427",
feature = "stm32f429",
feature = "stm32f437",
feature = "stm32f439",
feature = "stm32f446",
feature = "stm32f469",
feature = "stm32f479"
))]
exti!(gpiof, [
EXTI0 => PF0,
EXTI1 => PF1,
EXTI2 => PF2,
EXTI3 => PF3,
EXTI4 => PF4,
EXTI9_5 => PF5,
EXTI9_5 => PF6,
EXTI9_5 => PF7,
EXTI9_5 => PF8,
EXTI9_5 => PF9,
EXTI15_10 => PF10,
EXTI15_10 => PF11,
EXTI15_10 => PF12,
EXTI15_10 => PF13,
EXTI15_10 => PF14,
EXTI15_10 => PF15,
]);
#[cfg(any(
feature = "stm32f405",
feature = "stm32f407",
feature = "stm32f412",
feature = "stm32f413",
feature = "stm32f415",
feature = "stm32f417",
feature = "stm32f423",
feature = "stm32f427",
feature = "stm32f429",
feature = "stm32f437",
feature = "stm32f439",
feature = "stm32f446",
feature = "stm32f469",
feature = "stm32f479"
))]
exti!(gpiog, [
EXTI0 => PG0,
EXTI1 => PG1,
EXTI2 => PG2,
EXTI3 => PG3,
EXTI4 => PG4,
EXTI9_5 => PG5,
EXTI9_5 => PG6,
EXTI9_5 => PG7,
EXTI9_5 => PG8,
EXTI9_5 => PG9,
EXTI15_10 => PG10,
EXTI15_10 => PG11,
EXTI15_10 => PG12,
EXTI15_10 => PG13,
EXTI15_10 => PG14,
EXTI15_10 => PG15,
]);
#[cfg(any(
feature = "stm32f405",
feature = "stm32f407",
feature = "stm32f410",
feature = "stm32f411",
feature = "stm32f412",
feature = "stm32f413",
feature = "stm32f415",
feature = "stm32f417",
feature = "stm32f423",
feature = "stm32f427",
feature = "stm32f429",
feature = "stm32f437",
feature = "stm32f439",
feature = "stm32f446",
feature = "stm32f469",
feature = "stm32f479"
))]
exti!(gpioh, [
EXTI0 => PH0,
EXTI1 => PH1,
EXTI2 => PH2,
EXTI3 => PH3,
EXTI4 => PH4,
EXTI9_5 => PH5,
EXTI9_5 => PH6,
EXTI9_5 => PH7,
EXTI9_5 => PH8,
EXTI9_5 => PH9,
EXTI15_10 => PH10,
EXTI15_10 => PH11,
EXTI15_10 => PH12,
EXTI15_10 => PH13,
EXTI15_10 => PH14,
EXTI15_10 => PH15,
]);
#[cfg(any(feature = "stm32f401"))]
exti!(gpioh, [
EXTI0 => PH0,
EXTI1 => PH1,
]);
#[cfg(any(
feature = "stm32f405",
feature = "stm32f407",
feature = "stm32f415",
feature = "stm32f417",
feature = "stm32f427",
feature = "stm32f429",
feature = "stm32f437",
feature = "stm32f439",
feature = "stm32f469",
feature = "stm32f479"
))]
exti!(gpioi, [
EXTI0 => PI0,
EXTI1 => PI1,
EXTI2 => PI2,
EXTI3 => PI3,
EXTI4 => PI4,
EXTI9_5 => PI5,
EXTI9_5 => PI6,
EXTI9_5 => PI7,
EXTI9_5 => PI8,
EXTI9_5 => PI9,
EXTI15_10 => PI10,
EXTI15_10 => PI11,
EXTI15_10 => PI12,
EXTI15_10 => PI13,
EXTI15_10 => PI14,
EXTI15_10 => PI15,
]);
#[cfg(any(
feature = "stm32f427",
feature = "stm32f429",
feature = "stm32f437",
feature = "stm32f439",
feature = "stm32f469",
feature = "stm32f479"
))]
exti!(gpioj, [
EXTI0 => PJ0,
EXTI1 => PJ1,
EXTI2 => PJ2,
EXTI3 => PJ3,
EXTI4 => PJ4,
EXTI9_5 => PJ5,
EXTI9_5 => PJ6,
EXTI9_5 => PJ7,
EXTI9_5 => PJ8,
EXTI9_5 => PJ9,
EXTI15_10 => PJ10,
EXTI15_10 => PJ11,
EXTI15_10 => PJ12,
EXTI15_10 => PJ13,
EXTI15_10 => PJ14,
EXTI15_10 => PJ15,
]);
#[cfg(any(
feature = "stm32f427",
feature = "stm32f429",
feature = "stm32f437",
feature = "stm32f439",
feature = "stm32f469",
feature = "stm32f479"
))]
exti!(gpiok, [
EXTI0 => PK0,
EXTI1 => PK1,
EXTI2 => PK2,
EXTI3 => PK3,
EXTI4 => PK4,
EXTI9_5 => PK5,
EXTI9_5 => PK6,
EXTI9_5 => PK7,
]);

7
embassy-stm32f4/src/lib.rs
View File

@ -307,12 +307,11 @@ compile_error!(
"Multile chip features activated. You must activate exactly one of the following features: "
);
pub use embassy_stm32::{fmt, hal, interrupt, pac};
pub use embassy_stm32::{exti, fmt, hal, interrupt, pac, rtc};
#[cfg(not(any(feature = "stm32f401", feature = "stm32f410", feature = "stm32f411",)))]
pub mod can;
pub mod exti;
pub use embassy_stm32::can;
#[cfg(not(feature = "stm32f410"))]
pub mod qei;
pub mod rtc;
pub mod serial;

504
embassy-stm32f4/src/rtc.rs
View File

@ -1,504 +0,0 @@
use core::cell::Cell;
use core::convert::TryInto;
use core::sync::atomic::{compiler_fence, AtomicU32, Ordering};
use stm32f4xx_hal::bb;
use stm32f4xx_hal::rcc::Clocks;
use embassy::interrupt::InterruptExt;
use embassy::time::{Clock, TICKS_PER_SECOND};
use crate::interrupt;
use crate::interrupt::{CriticalSection, Interrupt, Mutex};
// RTC timekeeping works with something we call "periods", which are time intervals
// of 2^15 ticks. The RTC counter value is 16 bits, so one "overflow cycle" is 2 periods.
//
// A `period` count is maintained in parallel to the RTC hardware `counter`, like this:
// - `period` and `counter` start at 0
// - `period` is incremented on overflow (at counter value 0)
// - `period` is incremented "midway" between overflows (at counter value 0x8000)
//
// Therefore, when `period` is even, counter is in 0..0x7FFF. When odd, counter is in 0x8000..0xFFFF
// This allows for now() to return the correct value even if it races an overflow.
//
// To get `now()`, `period` is read first, then `counter` is read. If the counter value matches
// the expected range for the `period` parity, we're done. If it doesn't, this means that
// a new period start has raced us between reading `period` and `counter`, so we assume the `counter` value
// corresponds to the next period.
//
// `period` is a 32bit integer, so It overflows on 2^32 * 2^15 / 32768 seconds of uptime, which is 136 years.
fn calc_now(period: u32, counter: u16) -> u64 {
((period as u64) << 15) + ((counter as u32 ^ ((period & 1) << 15)) as u64)
}
struct AlarmState {
timestamp: Cell<u64>,
callback: Cell<Option<(fn(*mut ()), *mut ())>>,
}
impl AlarmState {
fn new() -> Self {
Self {
timestamp: Cell::new(u64::MAX),
callback: Cell::new(None),
}
}
}
// TODO: This is sometimes wasteful, try to find a better way
const ALARM_COUNT: usize = 3;
/// RTC timer that can be used by the executor and to set alarms.
///
/// It can work with Timers 2, 3, 4, 5, 9 and 12. Timers 9 and 12 only have one alarm available,
/// while the others have three each.
/// This timer works internally with a unit of 2^15 ticks, which means that if a call to
/// [`embassy::time::Clock::now`] is blocked for that amount of ticks the returned value will be
/// wrong (an old value). The current default tick rate is 32768 ticks per second.
pub struct RTC<T: Instance> {
rtc: T,
irq: T::Interrupt,
/// Number of 2^23 periods elapsed since boot.
period: AtomicU32,
/// Timestamp at which to fire alarm. u64::MAX if no alarm is scheduled.
alarms: Mutex<[AlarmState; ALARM_COUNT]>,
clocks: Clocks,
}
impl<T: Instance> RTC<T> {
pub fn new(rtc: T, irq: T::Interrupt, clocks: Clocks) -> Self {
Self {
rtc,
irq,
period: AtomicU32::new(0),
alarms: Mutex::new([AlarmState::new(), AlarmState::new(), AlarmState::new()]),
clocks,
}
}
pub fn start(&'static self) {
self.rtc.enable_clock();
self.rtc.stop_and_reset();
let multiplier = if T::ppre(&self.clocks) == 1 { 1 } else { 2 };
let freq = T::pclk(&self.clocks) * multiplier;
let psc = freq / TICKS_PER_SECOND as u32 - 1;
let psc: u16 = psc.try_into().unwrap();
self.rtc.set_psc_arr(psc, u16::MAX);
// Mid-way point
self.rtc.set_compare(0, 0x8000);
self.rtc.set_compare_interrupt(0, true);
self.irq.set_handler(|ptr| unsafe {
let this = &*(ptr as *const () as *const Self);
this.on_interrupt();
});
self.irq.set_handler_context(self as *const _ as *mut _);
self.irq.unpend();
self.irq.enable();
self.rtc.start();
}
fn on_interrupt(&self) {
if self.rtc.overflow_interrupt_status() {
self.rtc.overflow_clear_flag();
self.next_period();
}
// Half overflow
if self.rtc.compare_interrupt_status(0) {
self.rtc.compare_clear_flag(0);
self.next_period();
}
for n in 1..=ALARM_COUNT {
if self.rtc.compare_interrupt_status(n) {
self.rtc.compare_clear_flag(n);
interrupt::free(|cs| self.trigger_alarm(n, cs));
}
}
}
fn next_period(&self) {
interrupt::free(|cs| {
let period = self.period.fetch_add(1, Ordering::Relaxed) + 1;
let t = (period as u64) << 15;
for n in 1..=ALARM_COUNT {
let alarm = &self.alarms.borrow(cs)[n - 1];
let at = alarm.timestamp.get();
let diff = at - t;
if diff < 0xc000 {
self.rtc.set_compare(n, at as u16);
self.rtc.set_compare_interrupt(n, true);
}
}
})
}
fn trigger_alarm(&self, n: usize, cs: &CriticalSection) {
self.rtc.set_compare_interrupt(n, false);
let alarm = &self.alarms.borrow(cs)[n - 1];
alarm.timestamp.set(u64::MAX);
// Call after clearing alarm, so the callback can set another alarm.
if let Some((f, ctx)) = alarm.callback.get() {
f(ctx);
}
}
fn set_alarm_callback(&self, n: usize, callback: fn(*mut ()), ctx: *mut ()) {
interrupt::free(|cs| {
let alarm = &self.alarms.borrow(cs)[n - 1];
alarm.callback.set(Some((callback, ctx)));
})
}
fn set_alarm(&self, n: usize, timestamp: u64) {
interrupt::free(|cs| {
let alarm = &self.alarms.borrow(cs)[n - 1];
alarm.timestamp.set(timestamp);
let t = self.now();
if timestamp <= t {
self.trigger_alarm(n, cs);
return;
}
let diff = timestamp - t;
if diff < 0xc000 {
let safe_timestamp = timestamp.max(t + 3);
self.rtc.set_compare(n, safe_timestamp as u16);
self.rtc.set_compare_interrupt(n, true);
} else {
self.rtc.set_compare_interrupt(n, false);
}
})
}
pub fn alarm1(&'static self) -> Alarm<T> {
Alarm { n: 1, rtc: self }
}
pub fn alarm2(&'static self) -> Option<Alarm<T>> {
if T::REAL_ALARM_COUNT >= 2 {
Some(Alarm { n: 2, rtc: self })
} else {
None
}
}
pub fn alarm3(&'static self) -> Option<Alarm<T>> {
if T::REAL_ALARM_COUNT >= 3 {
Some(Alarm { n: 3, rtc: self })
} else {
None
}
}
}
impl<T: Instance> embassy::time::Clock for RTC<T> {
fn now(&self) -> u64 {
let period = self.period.load(Ordering::Relaxed);
compiler_fence(Ordering::Acquire);
let counter = self.rtc.counter();
calc_now(period, counter)
}
}
pub struct Alarm<T: Instance> {
n: usize,
rtc: &'static RTC<T>,
}
impl<T: Instance> embassy::time::Alarm for Alarm<T> {
fn set_callback(&self, callback: fn(*mut ()), ctx: *mut ()) {
self.rtc.set_alarm_callback(self.n, callback, ctx);
}
fn set(&self, timestamp: u64) {
self.rtc.set_alarm(self.n, timestamp);
}
fn clear(&self) {
self.rtc.set_alarm(self.n, u64::MAX);
}
}
mod sealed {
pub trait Sealed {}
}
pub trait Instance: sealed::Sealed + Sized + 'static {
type Interrupt: Interrupt;
const REAL_ALARM_COUNT: usize;
fn enable_clock(&self);
fn set_compare(&self, n: usize, value: u16);
fn set_compare_interrupt(&self, n: usize, enable: bool);
fn compare_interrupt_status(&self, n: usize) -> bool;
fn compare_clear_flag(&self, n: usize);
fn overflow_interrupt_status(&self) -> bool;
fn overflow_clear_flag(&self);
// This method should ensure that the values are really updated before returning
fn set_psc_arr(&self, psc: u16, arr: u16);
fn stop_and_reset(&self);
fn start(&self);
fn counter(&self) -> u16;
fn ppre(clocks: &Clocks) -> u8;
fn pclk(clocks: &Clocks) -> u32;
}
#[allow(unused_macros)]
macro_rules! impl_timer {
($module:ident: ($TYPE:ident, $INT:ident, $apbenr:ident, $enrbit:expr, $apbrstr:ident, $rstrbit:expr, $ppre:ident, $pclk: ident), 3) => {
mod $module {
use super::*;
use stm32f4xx_hal::pac::{$TYPE, RCC};
impl sealed::Sealed for $TYPE {}
impl Instance for $TYPE {
type Interrupt = interrupt::$INT;
const REAL_ALARM_COUNT: usize = 3;
fn enable_clock(&self) {
// NOTE(unsafe) It will only be used for atomic operations
unsafe {
let rcc = &*RCC::ptr();
bb::set(&rcc.$apbenr, $enrbit);
bb::set(&rcc.$apbrstr, $rstrbit);
bb::clear(&rcc.$apbrstr, $rstrbit);
}
}
fn set_compare(&self, n: usize, value: u16) {
// NOTE(unsafe) these registers accept all the range of u16 values
match n {
0 => self.ccr1.write(|w| unsafe { w.bits(value.into()) }),
1 => self.ccr2.write(|w| unsafe { w.bits(value.into()) }),
2 => self.ccr3.write(|w| unsafe { w.bits(value.into()) }),
3 => self.ccr4.write(|w| unsafe { w.bits(value.into()) }),
_ => {}
}
}
fn set_compare_interrupt(&self, n: usize, enable: bool) {
if n > 3 {
return;
}
let bit = n as u8 + 1;
unsafe {
if enable {
bb::set(&self.dier, bit);
} else {
bb::clear(&self.dier, bit);
}
}
}
fn compare_interrupt_status(&self, n: usize) -> bool {
let status = self.sr.read();
match n {
0 => status.cc1if().bit_is_set(),
1 => status.cc2if().bit_is_set(),
2 => status.cc3if().bit_is_set(),
3 => status.cc4if().bit_is_set(),
_ => false,
}
}
fn compare_clear_flag(&self, n: usize) {
if n > 3 {
return;
}
let bit = n as u8 + 1;
unsafe {
bb::clear(&self.sr, bit);
}
}
fn overflow_interrupt_status(&self) -> bool {
self.sr.read().uif().bit_is_set()
}
fn overflow_clear_flag(&self) {
unsafe {
bb::clear(&self.sr, 0);
}
}
fn set_psc_arr(&self, psc: u16, arr: u16) {
// NOTE(unsafe) All u16 values are valid
self.psc.write(|w| unsafe { w.bits(psc.into()) });
self.arr.write(|w| unsafe { w.bits(arr.into()) });
unsafe {
// Set URS, generate update, clear URS
bb::set(&self.cr1, 2);
self.egr.write(|w| w.ug().set_bit());
bb::clear(&self.cr1, 2);
}
}
fn stop_and_reset(&self) {
unsafe {
bb::clear(&self.cr1, 0);
}
self.cnt.reset();
}
fn start(&self) {
unsafe { bb::set(&self.cr1, 0) }
}
fn counter(&self) -> u16 {
self.cnt.read().bits() as u16
}
fn ppre(clocks: &Clocks) -> u8 {
clocks.$ppre()
}
fn pclk(clocks: &Clocks) -> u32 {
clocks.$pclk().0
}
}
}
};
($module:ident: ($TYPE:ident, $INT:ident, $apbenr:ident, $enrbit:expr, $apbrstr:ident, $rstrbit:expr, $ppre:ident, $pclk: ident), 1) => {
mod $module {
use super::*;
use stm32f4xx_hal::pac::{$TYPE, RCC};
impl sealed::Sealed for $TYPE {}
impl Instance for $TYPE {
type Interrupt = interrupt::$INT;
const REAL_ALARM_COUNT: usize = 1;
fn enable_clock(&self) {
// NOTE(unsafe) It will only be used for atomic operations
unsafe {
let rcc = &*RCC::ptr();
bb::set(&rcc.$apbenr, $enrbit);
bb::set(&rcc.$apbrstr, $rstrbit);
bb::clear(&rcc.$apbrstr, $rstrbit);
}
}
fn set_compare(&self, n: usize, value: u16) {
// NOTE(unsafe) these registers accept all the range of u16 values
match n {
0 => self.ccr1.write(|w| unsafe { w.bits(value.into()) }),
1 => self.ccr2.write(|w| unsafe { w.bits(value.into()) }),
_ => {}
}
}
fn set_compare_interrupt(&self, n: usize, enable: bool) {
if n > 1 {
return;
}
let bit = n as u8 + 1;
unsafe {
if enable {
bb::set(&self.dier, bit);
} else {
bb::clear(&self.dier, bit);
}
}
}
fn compare_interrupt_status(&self, n: usize) -> bool {
let status = self.sr.read();
match n {
0 => status.cc1if().bit_is_set(),
1 => status.cc2if().bit_is_set(),
_ => false,
}
}
fn compare_clear_flag(&self, n: usize) {
if n > 1 {
return;
}
let bit = n as u8 + 1;
unsafe {
bb::clear(&self.sr, bit);
}
}
fn overflow_interrupt_status(&self) -> bool {
self.sr.read().uif().bit_is_set()
}
fn overflow_clear_flag(&self) {
unsafe {
bb::clear(&self.sr, 0);
}
}
fn set_psc_arr(&self, psc: u16, arr: u16) {
// NOTE(unsafe) All u16 values are valid
self.psc.write(|w| unsafe { w.bits(psc.into()) });
self.arr.write(|w| unsafe { w.bits(arr.into()) });
unsafe {
// Set URS, generate update, clear URS
bb::set(&self.cr1, 2);
self.egr.write(|w| w.ug().set_bit());
bb::clear(&self.cr1, 2);
}
}
fn stop_and_reset(&self) {
unsafe {
bb::clear(&self.cr1, 0);
}
self.cnt.reset();
}
fn start(&self) {
unsafe { bb::set(&self.cr1, 0) }
}
fn counter(&self) -> u16 {
self.cnt.read().bits() as u16
}
fn ppre(clocks: &Clocks) -> u8 {
clocks.$ppre()
}
fn pclk(clocks: &Clocks) -> u32 {
clocks.$pclk().0
}
}
}
};
}
#[cfg(not(feature = "stm32f410"))]
impl_timer!(tim2: (TIM2, TIM2, apb1enr, 0, apb1rstr, 0, ppre1, pclk1), 3);
#[cfg(not(feature = "stm32f410"))]
impl_timer!(tim3: (TIM3, TIM3, apb1enr, 1, apb1rstr, 1, ppre1, pclk1), 3);
#[cfg(not(feature = "stm32f410"))]
impl_timer!(tim4: (TIM4, TIM4, apb1enr, 2, apb1rstr, 2, ppre1, pclk1), 3);
impl_timer!(tim5: (TIM5, TIM5, apb1enr, 3, apb1rstr, 3, ppre1, pclk1), 3);
impl_timer!(tim9: (TIM9, TIM1_BRK_TIM9, apb2enr, 16, apb2rstr, 16, ppre2, pclk2), 1);
#[cfg(not(any(feature = "stm32f401", feature = "stm32f410", feature = "stm32f411")))]
impl_timer!(tim12: (TIM12, TIM8_BRK_TIM12, apb1enr, 6, apb1rstr, 6, ppre1, pclk1), 1);

102
embassy-stm32f4/src/serial.rs
View File

@ -7,8 +7,10 @@
use core::future::Future;
use core::marker::PhantomData;
use futures::{select_biased, FutureExt};
use embassy::interrupt::Interrupt;
use embassy::traits::uart::{Error, Uart};
use embassy::traits::uart::{Error, IdleUart, Uart};
use embassy::util::InterruptFuture;
use crate::hal::{
@ -19,7 +21,7 @@ use crate::hal::{
rcc::Clocks,
serial,
serial::config::{Config as SerialConfig, DmaConfig as SerialDmaConfig},
serial::{Event as SerialEvent, Pins, Serial as HalSerial},
serial::{Event as SerialEvent, Pins},
};
use crate::interrupt;
use crate::pac;
@ -29,14 +31,14 @@ pub struct Serial<
USART: PeriAddress<MemSize = u8> + WithInterrupt,
TSTREAM: Stream + WithInterrupt,
RSTREAM: Stream + WithInterrupt,
CHANNEL: dma::traits::Channel,
CHANNEL: Channel,
> {
tx_stream: Option<TSTREAM>,
rx_stream: Option<RSTREAM>,
usart: Option<USART>,
tx_int: TSTREAM::Interrupt,
rx_int: RSTREAM::Interrupt,
_usart_int: USART::Interrupt,
usart_int: USART::Interrupt,
channel: PhantomData<CHANNEL>,
}
@ -68,12 +70,10 @@ where
PINS: Pins<USART>,
{
config.dma = SerialDmaConfig::TxRx;
let mut serial = HalSerial::new(usart, pins, config, clocks).unwrap();
serial.listen(SerialEvent::Idle);
// serial.listen(SerialEvent::Txe);
let (usart, _) = serial.release();
let (usart, _) = serial::Serial::new(usart, pins, config, clocks)
.unwrap()
.release();
let (tx_stream, rx_stream) = streams;
@ -83,8 +83,8 @@ where
usart: Some(usart),
tx_int: tx_int,
rx_int: rx_int,
_usart_int: usart_int,
channel: core::marker::PhantomData,
usart_int: usart_int,
channel: PhantomData,
}
}
}
@ -127,10 +127,10 @@ where
let fut = InterruptFuture::new(&mut self.tx_int);
tx_transfer.start(|_usart| {});
fut.await;
let (tx_stream, usart, _buf, _) = tx_transfer.free();
self.tx_stream.replace(tx_stream);
self.usart.replace(usart);
@ -163,7 +163,6 @@ where
);
let fut = InterruptFuture::new(&mut self.rx_int);
rx_transfer.start(|_usart| {});
fut.await;
@ -176,6 +175,79 @@ where
}
}
impl<USART, TSTREAM, RSTREAM, CHANNEL> IdleUart for Serial<USART, TSTREAM, RSTREAM, CHANNEL>
where
USART: serial::Instance
+ PeriAddress<MemSize = u8>
+ DMASet<TSTREAM, CHANNEL, MemoryToPeripheral>
+ DMASet<RSTREAM, CHANNEL, PeripheralToMemory>
+ WithInterrupt
+ 'static,
TSTREAM: Stream + WithInterrupt + 'static,
RSTREAM: Stream + WithInterrupt + 'static,
CHANNEL: Channel + 'static,
{
type ReceiveFuture<'a> = impl Future<Output = Result<usize, Error>> + 'a;
/// Receives serial data.
///
/// The future is pending until either the buffer is completely full, or the RX line falls idle after receiving some data.
///
/// Returns the number of bytes read.
fn receive_until_idle<'a>(&'a mut self, buf: &'a mut [u8]) -> Self::ReceiveFuture<'a> {
let static_buf = unsafe { core::mem::transmute::<&'a mut [u8], &'static mut [u8]>(buf) };
let rx_stream = self.rx_stream.take().unwrap();
let usart = self.usart.take().unwrap();
async move {
unsafe {
/* __HAL_UART_ENABLE_IT(&uart->UartHandle, UART_IT_IDLE); */
(*USART::ptr()).cr1.modify(|_, w| w.idleie().set_bit());
/* __HAL_UART_CLEAR_IDLEFLAG(&uart->UartHandle); */
(*USART::ptr()).sr.read();
(*USART::ptr()).dr.read();
};
let mut rx_transfer = Transfer::init(
rx_stream,
usart,
static_buf,
None,
DmaConfig::default()
.transfer_complete_interrupt(true)
.memory_increment(true)
.double_buffer(false),
);
let total_bytes = RSTREAM::get_number_of_transfers() as usize;
let fut = InterruptFuture::new(&mut self.rx_int);
let fut_idle = InterruptFuture::new(&mut self.usart_int);
rx_transfer.start(|_usart| {});
select_biased! {
() = fut.fuse() => {},
() = fut_idle.fuse() => {},
}
let (rx_stream, usart, _, _) = rx_transfer.free();
let remaining_bytes = RSTREAM::get_number_of_transfers() as usize;
unsafe {
(*USART::ptr()).cr1.modify(|_, w| w.idleie().clear_bit());
}
self.rx_stream.replace(rx_stream);
self.usart.replace(usart);
Ok(total_bytes - remaining_bytes)
}
}
}
mod private {
pub trait Sealed {}
}
@ -278,6 +350,6 @@ usart! {
UART4 => (UART4),
UART5 => (UART5),
UART7 => (UART7),
UART8 => (UART8),
// UART7 => (UART7),
// UART8 => (UART8),
}