rcc mux: update metapac
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@ -58,7 +58,7 @@ rand_core = "0.6.3"
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sdio-host = "0.5.0"
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sdio-host = "0.5.0"
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embedded-sdmmc = { git = "https://github.com/embassy-rs/embedded-sdmmc-rs", rev = "a4f293d3a6f72158385f79c98634cb8a14d0d2fc", optional = true }
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embedded-sdmmc = { git = "https://github.com/embassy-rs/embedded-sdmmc-rs", rev = "a4f293d3a6f72158385f79c98634cb8a14d0d2fc", optional = true }
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critical-section = "1.1"
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critical-section = "1.1"
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-6bfa5a0dcec6a9bd42cea94ba11eeae1a17a7f2c" }
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-e4a769aa67aa82603448377daa579d67a789983a" }
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vcell = "0.1.3"
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vcell = "0.1.3"
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bxcan = "0.7.0"
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bxcan = "0.7.0"
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nb = "1.0.0"
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nb = "1.0.0"
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@ -76,7 +76,7 @@ critical-section = { version = "1.1", features = ["std"] }
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[build-dependencies]
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[build-dependencies]
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proc-macro2 = "1.0.36"
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proc-macro2 = "1.0.36"
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quote = "1.0.15"
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quote = "1.0.15"
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-6bfa5a0dcec6a9bd42cea94ba11eeae1a17a7f2c", default-features = false, features = ["metadata"]}
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-e4a769aa67aa82603448377daa579d67a789983a", default-features = false, features = ["metadata"]}
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[features]
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[features]
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@ -5,7 +5,7 @@ use std::{env, fs};
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use proc_macro2::{Ident, TokenStream};
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use proc_macro2::{Ident, TokenStream};
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use quote::{format_ident, quote};
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use quote::{format_ident, quote};
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use stm32_metapac::metadata::ir::{BlockItemInner, Enum};
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use stm32_metapac::metadata::ir::{BlockItemInner, Enum, FieldSet};
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use stm32_metapac::metadata::{MemoryRegionKind, PeripheralRccRegister, METADATA};
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use stm32_metapac::metadata::{MemoryRegionKind, PeripheralRccRegister, METADATA};
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fn main() {
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fn main() {
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@ -400,29 +400,24 @@ fn main() {
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.ir;
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.ir;
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let rcc_blocks = rcc_registers.blocks.iter().find(|b| b.name == "Rcc").unwrap().items;
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let rcc_blocks = rcc_registers.blocks.iter().find(|b| b.name == "Rcc").unwrap().items;
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let rcc_fieldsets: HashMap<&str, &FieldSet> = rcc_registers.fieldsets.iter().map(|f| (f.name, f)).collect();
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let rcc_enums: HashMap<&str, &Enum> = rcc_registers.enums.iter().map(|e| (e.name, e)).collect();
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let rcc_block_item_map: HashMap<&str, &str> = rcc_blocks
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rcc_blocks
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.iter()
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.iter()
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.filter_map(|b| match &b.inner {
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.filter_map(|b| match &b.inner {
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BlockItemInner::Register(register) => register.fieldset.map(|f| (f, b.name)),
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BlockItemInner::Register(register) => register.fieldset.map(|f| (b.name, f)),
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_ => None,
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_ => None,
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})
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})
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.collect();
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.filter_map(|(b, f)| {
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rcc_fieldsets.get(f).map(|f| {
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let rcc_enum_map: HashMap<&str, &Enum> = rcc_registers.enums.iter().map(|e| (e.name, e)).collect();
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rcc_registers
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.fieldsets
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.iter()
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.filter_map(|f| {
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rcc_block_item_map.get(f.name).map(|b| {
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(
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(
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*b,
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b,
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f.fields
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f.fields
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.iter()
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.iter()
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.filter_map(|f| {
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.filter_map(|f| {
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let enumm = f.enumm?;
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let enumm = f.enumm?;
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let enumm = rcc_enum_map.get(enumm)?;
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let enumm = rcc_enums.get(enumm)?;
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Some((f.name, *enumm))
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Some((f.name, *enumm))
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})
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})
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@ -457,8 +457,8 @@ pub(crate) unsafe fn init(config: Config) {
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AdcClockSource::SYSCLK => Some(sys),
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AdcClockSource::SYSCLK => Some(sys),
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AdcClockSource::PLL2_R => pll2.r,
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AdcClockSource::PLL2_R => pll2.r,
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AdcClockSource::HSE => hse,
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AdcClockSource::HSE => hse,
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AdcClockSource::HSI_KER => hsi,
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AdcClockSource::HSI => hsi,
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AdcClockSource::CSI_KER => csi,
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AdcClockSource::CSI => csi,
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_ => unreachable!(),
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_ => unreachable!(),
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};
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};
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@ -547,15 +547,25 @@ pub(crate) unsafe fn init(config: Config) {
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rtc,
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rtc,
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#[cfg(stm32h5)]
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#[cfg(stm32h5)]
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mux_rcc_pclk1: Some(apb1),
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mux_apb1: Some(apb1),
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#[cfg(stm32h5)]
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mux_apb2: Some(apb2),
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#[cfg(stm32h5)]
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mux_apb3: Some(apb3),
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#[cfg(stm32h5)]
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mux_apb4: None,
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#[cfg(stm32h5)]
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mux_rcc_hclk4: None,
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#[cfg(stm32h5)]
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#[cfg(stm32h5)]
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mux_pll2_q: None,
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mux_pll2_q: None,
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#[cfg(stm32h5)]
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#[cfg(stm32h5)]
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mux_pll3_q: None,
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mux_pll3_q: None,
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#[cfg(stm32h5)]
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#[cfg(stm32h5)]
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mux_hsi_ker: None,
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mux_hsi: None,
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#[cfg(stm32h5)]
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#[cfg(stm32h5)]
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mux_csi_ker: None,
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mux_csi: None,
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#[cfg(stm32h5)]
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#[cfg(stm32h5)]
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mux_lse: None,
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mux_lse: None,
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#[cfg(stm32h5)]
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#[cfg(stm32h5)]
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@ -574,20 +584,14 @@ pub(crate) unsafe fn init(config: Config) {
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#[cfg(all(not(rcc_h5), stm32h5))]
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#[cfg(all(not(rcc_h5), stm32h5))]
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mux_pll3_r: None,
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mux_pll3_r: None,
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#[cfg(stm32h5)]
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#[cfg(stm32h5)]
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mux_rcc_pclk3: Some(apb3),
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#[cfg(stm32h5)]
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mux_pll3_1: None,
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mux_pll3_1: None,
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#[cfg(stm32h5)]
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#[cfg(stm32h5)]
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mux_hsi48_ker: None,
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mux_hsi48_ker: None,
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#[cfg(stm32h5)]
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#[cfg(stm32h5)]
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mux_lsi_ker: None,
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mux_lsi: None,
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#[cfg(stm32h5)]
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#[cfg(stm32h5)]
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mux_pll2_r: pll2.r,
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mux_pll2_r: pll2.r,
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#[cfg(stm32h5)]
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#[cfg(stm32h5)]
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mux_rcc_pclk2: Some(apb2),
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#[cfg(stm32h5)]
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mux_rcc_pclk4: None,
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#[cfg(stm32h5)]
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mux_hse: hse,
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mux_hse: hse,
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#[cfg(stm32h5)]
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#[cfg(stm32h5)]
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@ -136,15 +136,25 @@ pub struct Clocks {
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pub rtc: Option<Hertz>,
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pub rtc: Option<Hertz>,
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#[cfg(stm32h5)]
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#[cfg(stm32h5)]
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pub mux_rcc_pclk1: Option<Hertz>,
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pub mux_apb1: Option<Hertz>,
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#[cfg(stm32h5)]
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pub mux_apb2: Option<Hertz>,
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#[cfg(stm32h5)]
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pub mux_apb3: Option<Hertz>,
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#[cfg(stm32h5)]
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pub mux_apb4: Option<Hertz>,
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#[cfg(stm32h5)]
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pub mux_rcc_hclk4: Option<Hertz>,
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#[cfg(stm32h5)]
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#[cfg(stm32h5)]
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pub mux_pll2_q: Option<Hertz>,
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pub mux_pll2_q: Option<Hertz>,
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#[cfg(stm32h5)]
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#[cfg(stm32h5)]
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pub mux_pll3_q: Option<Hertz>,
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pub mux_pll3_q: Option<Hertz>,
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#[cfg(stm32h5)]
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#[cfg(stm32h5)]
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pub mux_hsi_ker: Option<Hertz>,
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pub mux_hsi: Option<Hertz>,
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#[cfg(stm32h5)]
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#[cfg(stm32h5)]
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pub mux_csi_ker: Option<Hertz>,
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pub mux_csi: Option<Hertz>,
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#[cfg(stm32h5)]
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#[cfg(stm32h5)]
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pub mux_lse: Option<Hertz>,
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pub mux_lse: Option<Hertz>,
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@ -162,20 +172,14 @@ pub struct Clocks {
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#[cfg(stm32h5)]
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#[cfg(stm32h5)]
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pub mux_pll3_r: Option<Hertz>,
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pub mux_pll3_r: Option<Hertz>,
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#[cfg(stm32h5)]
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#[cfg(stm32h5)]
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pub mux_rcc_pclk3: Option<Hertz>,
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#[cfg(stm32h5)]
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pub mux_pll3_1: Option<Hertz>,
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pub mux_pll3_1: Option<Hertz>,
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#[cfg(stm32h5)]
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#[cfg(stm32h5)]
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pub mux_hsi48_ker: Option<Hertz>,
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pub mux_hsi48_ker: Option<Hertz>,
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#[cfg(stm32h5)]
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#[cfg(stm32h5)]
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pub mux_lsi_ker: Option<Hertz>,
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pub mux_lsi: Option<Hertz>,
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#[cfg(stm32h5)]
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#[cfg(stm32h5)]
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pub mux_pll2_r: Option<Hertz>,
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pub mux_pll2_r: Option<Hertz>,
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#[cfg(stm32h5)]
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#[cfg(stm32h5)]
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pub mux_rcc_pclk2: Option<Hertz>,
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#[cfg(stm32h5)]
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pub mux_rcc_pclk4: Option<Hertz>,
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#[cfg(stm32h5)]
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pub mux_hse: Option<Hertz>,
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pub mux_hse: Option<Hertz>,
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#[cfg(stm32h5)]
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#[cfg(stm32h5)]
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