diff --git a/embassy-net-adin1110/src/mdio.rs b/embassy-net-adin1110/src/mdio.rs
index 60abbe16..1ae5f004 100644
--- a/embassy-net-adin1110/src/mdio.rs
+++ b/embassy-net-adin1110/src/mdio.rs
@@ -32,6 +32,7 @@ enum Reg13Op {
PostReadIncAddr = 0b10 << 14,
Read = 0b11 << 14,
}
+
/// `MdioBus` trait
/// Driver needs to implement the Clause 22
/// Optional Clause 45 is the device supports this.
@@ -87,89 +88,89 @@ pub trait MdioBus {
}
}
-// #[cfg(test)]
-// mod tests {
-// use core::convert::Infallible;
+#[cfg(test)]
+mod tests {
+ use core::convert::Infallible;
-// use super::{MdioBus, PhyAddr, RegC22, RegVal};
+ use super::{MdioBus, PhyAddr, RegC22, RegVal};
-// #[derive(Debug, PartialEq, Eq)]
-// enum A {
-// Read(PhyAddr, RegC22),
-// Write(PhyAddr, RegC22, RegVal),
-// }
+ #[derive(Debug, PartialEq, Eq)]
+ enum A {
+ Read(PhyAddr, RegC22),
+ Write(PhyAddr, RegC22, RegVal),
+ }
-// struct MockMdioBus(Vec);
+ struct MockMdioBus(Vec);
-// impl MockMdioBus {
-// pub fn clear(&mut self) {
-// self.0.clear();
-// }
-// }
+ impl MockMdioBus {
+ pub fn clear(&mut self) {
+ self.0.clear();
+ }
+ }
-// impl MdioBus for MockMdioBus {
-// type Error = Infallible;
+ impl MdioBus for MockMdioBus {
+ type Error = Infallible;
-// fn write_cl22(
-// &mut self,
-// phy_id: super::PhyAddr,
-// reg: super::RegC22,
-// reg_val: super::RegVal,
-// ) -> Result<(), Self::Error> {
-// self.0.push(A::Write(phy_id, reg, reg_val));
-// Ok(())
-// }
+ async fn write_cl22(
+ &mut self,
+ phy_id: super::PhyAddr,
+ reg: super::RegC22,
+ reg_val: super::RegVal,
+ ) -> Result<(), Self::Error> {
+ self.0.push(A::Write(phy_id, reg, reg_val));
+ Ok(())
+ }
-// fn read_cl22(
-// &mut self,
-// phy_id: super::PhyAddr,
-// reg: super::RegC22,
-// ) -> Result {
-// self.0.push(A::Read(phy_id, reg));
-// Ok(0)
-// }
-// }
+ async fn read_cl22(
+ &mut self,
+ phy_id: super::PhyAddr,
+ reg: super::RegC22,
+ ) -> Result {
+ self.0.push(A::Read(phy_id, reg));
+ Ok(0)
+ }
+ }
-// #[test]
-// fn read_test() {
-// let mut mdiobus = MockMdioBus(Vec::with_capacity(20));
+ #[futures_test::test]
+ async fn read_test() {
+ let mut mdiobus = MockMdioBus(Vec::with_capacity(20));
-// mdiobus.clear();
-// mdiobus.read_cl22(0x01, 0x00).unwrap();
-// assert_eq!(mdiobus.0, vec![A::Read(0x01, 0x00)]);
+ mdiobus.clear();
+ mdiobus.read_cl22(0x01, 0x00).await.unwrap();
+ assert_eq!(mdiobus.0, vec![A::Read(0x01, 0x00)]);
-// mdiobus.clear();
-// mdiobus.read_cl45(0x01, (0xBB, 0x1234)).unwrap();
-// assert_eq!(
-// mdiobus.0,
-// vec![
-// #[allow(clippy::identity_op)]
-// A::Write(0x01, 13, (0b00 << 14) | 27),
-// A::Write(0x01, 14, 0x1234),
-// A::Write(0x01, 13, (0b11 << 14) | 27),
-// A::Read(0x01, 14)
-// ]
-// );
-// }
+ mdiobus.clear();
+ mdiobus.read_cl45(0x01, (0xBB, 0x1234)).await.unwrap();
+ assert_eq!(
+ mdiobus.0,
+ vec![
+ #[allow(clippy::identity_op)]
+ A::Write(0x01, 13, (0b00 << 14) | 27),
+ A::Write(0x01, 14, 0x1234),
+ A::Write(0x01, 13, (0b11 << 14) | 27),
+ A::Read(0x01, 14)
+ ]
+ );
+ }
-// #[test]
-// fn write_test() {
-// let mut mdiobus = MockMdioBus(Vec::with_capacity(20));
+ #[futures_test::test]
+ async fn write_test() {
+ let mut mdiobus = MockMdioBus(Vec::with_capacity(20));
-// mdiobus.clear();
-// mdiobus.write_cl22(0x01, 0x00, 0xABCD).unwrap();
-// assert_eq!(mdiobus.0, vec![A::Write(0x01, 0x00, 0xABCD)]);
+ mdiobus.clear();
+ mdiobus.write_cl22(0x01, 0x00, 0xABCD).await.unwrap();
+ assert_eq!(mdiobus.0, vec![A::Write(0x01, 0x00, 0xABCD)]);
-// mdiobus.clear();
-// mdiobus.write_cl45(0x01, (0xBB, 0x1234), 0xABCD).unwrap();
-// assert_eq!(
-// mdiobus.0,
-// vec![
-// A::Write(0x01, 13, 27),
-// A::Write(0x01, 14, 0x1234),
-// A::Write(0x01, 13, (0b01 << 14) | 27),
-// A::Write(0x01, 14, 0xABCD)
-// ]
-// );
-// }
-// }
+ mdiobus.clear();
+ mdiobus.write_cl45(0x01, (0xBB, 0x1234), 0xABCD).await.unwrap();
+ assert_eq!(
+ mdiobus.0,
+ vec![
+ A::Write(0x01, 13, 27),
+ A::Write(0x01, 14, 0x1234),
+ A::Write(0x01, 13, (0b01 << 14) | 27),
+ A::Write(0x01, 14, 0xABCD)
+ ]
+ );
+ }
+}