Dario Nieuwenhuis
GitHub
commit
3835278567
@ -9,7 +9,7 @@ fn main() {
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.expect("No stm32xx Cargo feature enabled")
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.strip_prefix("CARGO_FEATURE_")
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.unwrap()
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.to_ascii_uppercase();
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.to_ascii_lowercase();
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let out_dir = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
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let out_file = out_dir.join("generated.rs").to_string_lossy().to_string();
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@ -30,6 +30,15 @@ fn main() {
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};
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);
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let mut chip_and_core = chip_name.split('_');
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let chip = chip_and_core.next().expect("Unexpected stm32xx feature");
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if let Some(core) = chip_and_core.next() {
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println!("cargo:rustc-cfg={}_{}", &chip[..(chip.len() - 2)], core);
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} else {
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println!("cargo:rustc-cfg={}", &chip[..(chip.len() - 2)]);
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}
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println!("cargo:rerun-if-changed=build.rs");
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println!("cargo:rerun-if-changed=gen.py");
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}
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1
embassy-stm32/src/pwr/f4.rs
Normal file
1
embassy-stm32/src/pwr/f4.rs
Normal file
@ -0,0 +1 @@
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@ -1,4 +1,5 @@
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#[cfg_attr(any(pwr_h7, pwr_h7smps), path = "h7.rs")]
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#[cfg_attr(pwr_f4, path = "f4.rs")]
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mod _version;
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pub use _version::*;
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21
embassy-stm32/src/rcc/f4/max.rs
Normal file
21
embassy-stm32/src/rcc/f4/max.rs
Normal file
@ -0,0 +1,21 @@
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#[cfg(stm32f401)]
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pub(crate) const SYSCLK_MAX: u32 = 84_000_000;
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#[cfg(any(stm32f405, stm32f407, stm32f415, stm32f417,))]
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pub(crate) const SYSCLK_MAX: u32 = 168_000_000;
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#[cfg(any(stm32f410, stm32f411, stm32f412, stm32f413, stm32f423,))]
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pub(crate) const SYSCLK_MAX: u32 = 100_000_000;
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#[cfg(any(
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stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479,
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))]
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pub(crate) const SYSCLK_MAX: u32 = 180_000_000;
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#[cfg(any(stm32f401, stm32f410, stm32f411, stm32f412, stm32f413, stm32f423,))]
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pub(crate) const PCLK2_MAX: u32 = SYSCLK_MAX;
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#[cfg(not(any(stm32f401, stm32f410, stm32f411, stm32f412, stm32f413, stm32f423,)))]
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pub(crate) const PCLK2_MAX: u32 = SYSCLK_MAX / 2;
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pub(crate) const PCLK1_MAX: u32 = PCLK2_MAX / 2;
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@ -1,207 +1,325 @@
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pub use super::types::*;
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use crate::pac;
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use crate::peripherals::{self, RCC};
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use crate::pac::{FLASH, PWR, RCC};
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use crate::peripherals;
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use crate::rcc::{get_freqs, set_freqs, Clocks};
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use crate::time::Hertz;
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use crate::time::U32Ext;
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use core::marker::PhantomData;
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use embassy::util::Unborrow;
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use embassy_hal_common::unborrow;
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use pac::rcc::vals::{Hpre, Ppre, Sw};
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/// Most of clock setup is copied from stm32l0xx-hal, and adopted to the generated PAC,
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/// and with the addition of the init function to configure a system clock.
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mod max;
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use max::{PCLK1_MAX, PCLK2_MAX};
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/// Only the basic setup using the HSE and HSI clocks are supported as of now.
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/// HSI speed
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pub const HSI_FREQ: u32 = 16_000_000;
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/// System clock mux source
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#[derive(Clone, Copy)]
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pub enum ClockSrc {
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HSE(Hertz),
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HSI16,
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}
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impl Into<Ppre> for APBPrescaler {
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fn into(self) -> Ppre {
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match self {
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APBPrescaler::NotDivided => Ppre::DIV1,
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APBPrescaler::Div2 => Ppre::DIV2,
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APBPrescaler::Div4 => Ppre::DIV4,
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APBPrescaler::Div8 => Ppre::DIV8,
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APBPrescaler::Div16 => Ppre::DIV16,
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}
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}
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}
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impl Into<Hpre> for AHBPrescaler {
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fn into(self) -> Hpre {
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match self {
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AHBPrescaler::NotDivided => Hpre::DIV1,
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AHBPrescaler::Div2 => Hpre::DIV2,
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AHBPrescaler::Div4 => Hpre::DIV4,
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AHBPrescaler::Div8 => Hpre::DIV8,
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AHBPrescaler::Div16 => Hpre::DIV16,
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AHBPrescaler::Div64 => Hpre::DIV64,
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AHBPrescaler::Div128 => Hpre::DIV128,
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AHBPrescaler::Div256 => Hpre::DIV256,
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AHBPrescaler::Div512 => Hpre::DIV512,
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}
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}
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}
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const HSI: u32 = 16_000_000;
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/// Clocks configutation
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#[non_exhaustive]
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#[derive(Default)]
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pub struct Config {
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mux: ClockSrc,
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ahb_pre: AHBPrescaler,
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apb1_pre: APBPrescaler,
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apb2_pre: APBPrescaler,
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}
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impl Default for Config {
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#[inline]
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fn default() -> Config {
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Config {
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mux: ClockSrc::HSI16,
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ahb_pre: AHBPrescaler::NotDivided,
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apb1_pre: APBPrescaler::NotDivided,
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apb2_pre: APBPrescaler::NotDivided,
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}
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}
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}
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impl Config {
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#[inline]
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pub fn clock_src(mut self, mux: ClockSrc) -> Self {
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self.mux = mux;
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self
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}
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#[inline]
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pub fn ahb_pre(mut self, pre: AHBPrescaler) -> Self {
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self.ahb_pre = pre;
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self
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}
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#[inline]
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pub fn apb1_pre(mut self, pre: APBPrescaler) -> Self {
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self.apb1_pre = pre;
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self
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}
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#[inline]
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pub fn apb2_pre(mut self, pre: APBPrescaler) -> Self {
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self.apb2_pre = pre;
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self
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}
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pub hse: Option<Hertz>,
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pub bypass_hse: bool,
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pub pll48: bool,
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pub sys_ck: Option<Hertz>,
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pub hclk: Option<Hertz>,
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pub pclk1: Option<Hertz>,
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pub pclk2: Option<Hertz>,
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pub enable_debug_wfe: bool,
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}
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/// RCC peripheral
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pub struct Rcc<'d> {
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_rb: peripherals::RCC,
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config: Config,
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phantom: PhantomData<&'d mut peripherals::RCC>,
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}
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impl<'d> Rcc<'d> {
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pub fn new(rcc: impl Unborrow<Target = peripherals::RCC> + 'd) -> Self {
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unborrow!(rcc);
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pub fn new(_rcc: impl Unborrow<Target = peripherals::RCC> + 'd, config: Config) -> Self {
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Self {
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_rb: rcc,
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config,
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phantom: PhantomData,
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}
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}
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fn freeze(mut self) -> Clocks {
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use super::sealed::RccPeripheral;
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use crate::pac::rcc::vals::{Hpre, Hsebyp, Ppre, Sw};
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let pllsrcclk = self.config.hse.map(|hse| hse.0).unwrap_or(HSI);
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let sysclk = self.config.sys_ck.map(|sys| sys.0).unwrap_or(pllsrcclk);
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let sysclk_on_pll = sysclk != pllsrcclk;
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let plls = self.setup_pll(
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pllsrcclk,
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self.config.hse.is_some(),
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if sysclk_on_pll { Some(sysclk) } else { None },
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self.config.pll48,
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);
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if self.config.pll48 {
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assert!(
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// USB specification allows +-0.25%
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plls.pll48clk
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.map(|freq| (48_000_000 - freq as i32).abs() <= 120_000)
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.unwrap_or(false)
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);
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}
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let sysclk = if sysclk_on_pll {
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plls.pllsysclk.unwrap()
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} else {
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sysclk
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};
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let hclk = self.config.hclk.map(|h| h.0).unwrap_or(sysclk);
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let (hpre_bits, hpre_div) = match (sysclk + hclk - 1) / hclk {
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0 => unreachable!(),
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1 => (Hpre::DIV1, 1),
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2 => (Hpre::DIV2, 2),
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3..=5 => (Hpre::DIV4, 4),
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6..=11 => (Hpre::DIV8, 8),
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12..=39 => (Hpre::DIV16, 16),
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40..=95 => (Hpre::DIV64, 64),
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96..=191 => (Hpre::DIV128, 128),
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192..=383 => (Hpre::DIV256, 256),
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_ => (Hpre::DIV512, 512),
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};
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// Calculate real AHB clock
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let hclk = sysclk / hpre_div;
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let pclk1 = self
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.config
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.pclk1
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.map(|p| p.0)
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.unwrap_or_else(|| core::cmp::min(PCLK1_MAX, hclk));
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let (ppre1_bits, ppre1) = match (hclk + pclk1 - 1) / pclk1 {
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0 => unreachable!(),
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1 => (0b000, 1),
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2 => (0b100, 2),
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3..=5 => (0b101, 4),
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6..=11 => (0b110, 8),
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_ => (0b111, 16),
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};
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let timer_mul1 = if ppre1 == 1 { 1 } else { 2 };
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// Calculate real APB1 clock
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let pclk1 = hclk / ppre1;
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assert!(pclk1 <= PCLK1_MAX);
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let pclk2 = self
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.config
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.pclk2
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.map(|p| p.0)
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.unwrap_or_else(|| core::cmp::min(PCLK2_MAX, hclk));
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let (ppre2_bits, ppre2) = match (hclk + pclk2 - 1) / pclk2 {
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0 => unreachable!(),
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1 => (0b000, 1),
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2 => (0b100, 2),
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3..=5 => (0b101, 4),
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6..=11 => (0b110, 8),
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_ => (0b111, 16),
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};
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let timer_mul2 = if ppre2 == 1 { 1 } else { 2 };
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// Calculate real APB2 clock
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let pclk2 = hclk / ppre2;
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assert!(pclk2 <= PCLK2_MAX);
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Self::flash_setup(sysclk);
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if self.config.hse.is_some() {
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// NOTE(unsafe) We own the peripheral block
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unsafe {
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RCC.cr().modify(|w| {
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w.set_hsebyp(Hsebyp(self.config.bypass_hse as u8));
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w.set_hseon(true);
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});
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while !RCC.cr().read().hserdy() {}
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}
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}
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if plls.use_pll {
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unsafe {
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RCC.cr().modify(|w| w.set_pllon(true));
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if hclk > 168_000_000 {
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peripherals::PWR::enable();
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PWR.cr().modify(|w| w.set_oden(true));
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while !PWR.csr().read().odrdy() {}
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PWR.cr().modify(|w| w.set_odswen(true));
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while !PWR.csr().read().odswrdy() {}
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}
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while !RCC.cr().read().pllrdy() {}
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}
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}
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unsafe {
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RCC.cfgr().modify(|w| {
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w.set_ppre2(Ppre(ppre2_bits));
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w.set_ppre1(Ppre(ppre1_bits));
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w.set_hpre(hpre_bits);
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});
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// Wait for the new prescalers to kick in
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// "The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after write"
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cortex_m::asm::delay(16);
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RCC.cfgr().modify(|w| {
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w.set_sw(if sysclk_on_pll {
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Sw::PLL
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} else if self.config.hse.is_some() {
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Sw::HSE
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} else {
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Sw::HSI
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})
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});
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}
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if self.config.enable_debug_wfe {
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unsafe {
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RCC.ahb1enr().modify(|w| w.set_dma1en(true));
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critical_section::with(|_| {
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crate::dbgmcu::Dbgmcu::enable_all();
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});
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}
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}
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Clocks {
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sys: Hertz(sysclk),
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apb1: Hertz(pclk1),
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apb2: Hertz(pclk2),
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apb1_tim: Hertz(pclk1 * timer_mul1),
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apb2_tim: Hertz(pclk2 * timer_mul2),
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ahb1: Hertz(hclk),
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ahb2: Hertz(hclk),
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ahb3: Hertz(hclk),
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pll48: plls.pll48clk.map(Hertz),
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}
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}
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// Safety: RCC init must have been called
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pub fn clocks(&self) -> &'static Clocks {
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unsafe { get_freqs() }
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}
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}
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/// Extension trait that freezes the `RCC` peripheral with provided clocks configuration
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pub trait RccExt {
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fn freeze(self, config: Config) -> Clocks;
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}
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fn setup_pll(
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&mut self,
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pllsrcclk: u32,
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use_hse: bool,
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pllsysclk: Option<u32>,
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pll48clk: bool,
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) -> PllResults {
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use crate::pac::rcc::vals::{Pllp, Pllsrc};
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impl RccExt for RCC {
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#[inline]
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fn freeze(self, cfgr: Config) -> Clocks {
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let rcc = pac::RCC;
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let (sys_clk, sw) = match cfgr.mux {
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ClockSrc::HSI16 => {
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// Enable HSI16
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let sysclk = pllsysclk.unwrap_or(pllsrcclk);
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if pllsysclk.is_none() && !pll48clk {
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// NOTE(unsafe) We have a mutable borrow to the owner of the RegBlock
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unsafe {
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rcc.cr().modify(|w| w.set_hsion(true));
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while !rcc.cr().read().hsirdy() {}
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RCC.pllcfgr()
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.modify(|w| w.set_pllsrc(Pllsrc(use_hse as u8)));
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}
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(HSI_FREQ, Sw::HSI)
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}
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ClockSrc::HSE(freq) => {
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// Enable HSE
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unsafe {
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rcc.cr().modify(|w| w.set_hseon(true));
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while !rcc.cr().read().hserdy() {}
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return PllResults {
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use_pll: false,
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pllsysclk: None,
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pll48clk: None,
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};
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}
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// Input divisor from PLL source clock, must result to frequency in
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// the range from 1 to 2 MHz
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let pllm_min = (pllsrcclk + 1_999_999) / 2_000_000;
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let pllm_max = pllsrcclk / 1_000_000;
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(freq.0, Sw::HSE)
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}
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// Sysclk output divisor must be one of 2, 4, 6 or 8
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let sysclk_div = core::cmp::min(8, (432_000_000 / sysclk) & !1);
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let target_freq = if pll48clk {
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48_000_000
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} else {
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sysclk * sysclk_div
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};
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// Find the lowest pllm value that minimize the difference between
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// target frequency and the real vco_out frequency.
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let pllm = (pllm_min..=pllm_max)
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.min_by_key(|pllm| {
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let vco_in = pllsrcclk / pllm;
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let plln = target_freq / vco_in;
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target_freq - vco_in * plln
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})
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.unwrap();
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let vco_in = pllsrcclk / pllm;
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assert!((1_000_000..=2_000_000).contains(&vco_in));
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// Main scaler, must result in >= 100MHz (>= 192MHz for F401)
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// and <= 432MHz, min 50, max 432
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let plln = if pll48clk {
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// try the different valid pllq according to the valid
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// main scaller values, and take the best
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let pllq = (4..=9)
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.min_by_key(|pllq| {
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let plln = 48_000_000 * pllq / vco_in;
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let pll48_diff = 48_000_000 - vco_in * plln / pllq;
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let sysclk_diff = (sysclk as i32 - (vco_in * plln / sysclk_div) as i32).abs();
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(pll48_diff, sysclk_diff)
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})
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.unwrap();
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48_000_000 * pllq / vco_in
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} else {
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sysclk * sysclk_div / vco_in
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};
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let pllp = (sysclk_div / 2) - 1;
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let pllq = (vco_in * plln + 47_999_999) / 48_000_000;
|
||||
let real_pll48clk = vco_in * plln / pllq;
|
||||
|
||||
unsafe {
|
||||
rcc.cfgr().modify(|w| {
|
||||
w.set_sw(sw.into());
|
||||
w.set_hpre(cfgr.ahb_pre.into());
|
||||
w.set_ppre1(cfgr.apb1_pre.into());
|
||||
w.set_ppre2(cfgr.apb2_pre.into());
|
||||
RCC.pllcfgr().modify(|w| {
|
||||
w.set_pllm(pllm as u8);
|
||||
w.set_plln(plln as u16);
|
||||
w.set_pllp(Pllp(pllp as u8));
|
||||
w.set_pllq(pllq as u8);
|
||||
w.set_pllsrc(Pllsrc(use_hse as u8));
|
||||
});
|
||||
}
|
||||
|
||||
let ahb_freq: u32 = match cfgr.ahb_pre {
|
||||
AHBPrescaler::NotDivided => sys_clk,
|
||||
pre => {
|
||||
let pre: Hpre = pre.into();
|
||||
let pre = 1 << (pre.0 as u32 - 7);
|
||||
sys_clk / pre
|
||||
}
|
||||
};
|
||||
let real_pllsysclk = vco_in * plln / sysclk_div;
|
||||
|
||||
let (apb1_freq, apb1_tim_freq) = match cfgr.apb1_pre {
|
||||
APBPrescaler::NotDivided => (ahb_freq, ahb_freq),
|
||||
pre => {
|
||||
let pre: Ppre = pre.into();
|
||||
let pre: u8 = 1 << (pre.0 - 3);
|
||||
let freq = ahb_freq / pre as u32;
|
||||
(freq, freq * 2)
|
||||
PllResults {
|
||||
use_pll: true,
|
||||
pllsysclk: Some(real_pllsysclk),
|
||||
pll48clk: if pll48clk { Some(real_pll48clk) } else { None },
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
let (apb2_freq, apb2_tim_freq) = match cfgr.apb2_pre {
|
||||
APBPrescaler::NotDivided => (ahb_freq, ahb_freq),
|
||||
pre => {
|
||||
let pre: Ppre = pre.into();
|
||||
let pre: u8 = 1 << (pre.0 - 3);
|
||||
let freq = ahb_freq / (1 << (pre as u8 - 3));
|
||||
(freq, freq * 2)
|
||||
}
|
||||
};
|
||||
fn flash_setup(sysclk: u32) {
|
||||
use crate::pac::flash::vals::Latency;
|
||||
|
||||
Clocks {
|
||||
sys: sys_clk.hz(),
|
||||
ahb1: ahb_freq.hz(),
|
||||
ahb2: ahb_freq.hz(),
|
||||
ahb3: ahb_freq.hz(),
|
||||
apb1: apb1_freq.hz(),
|
||||
apb2: apb2_freq.hz(),
|
||||
apb1_tim: apb1_tim_freq.hz(),
|
||||
apb2_tim: apb2_tim_freq.hz(),
|
||||
}
|
||||
// Be conservative with voltage ranges
|
||||
const FLASH_LATENCY_STEP: u32 = 30_000_000;
|
||||
|
||||
critical_section::with(|_| unsafe {
|
||||
FLASH
|
||||
.acr()
|
||||
.modify(|w| w.set_latency(Latency(((sysclk - 1) / FLASH_LATENCY_STEP) as u8)));
|
||||
});
|
||||
}
|
||||
}
|
||||
|
||||
pub unsafe fn init(config: Config) {
|
||||
let r = <peripherals::RCC as embassy::util::Steal>::steal();
|
||||
let clocks = r.freeze(config);
|
||||
let clocks = Rcc::new(r, config).freeze();
|
||||
set_freqs(clocks);
|
||||
}
|
||||
|
||||
struct PllResults {
|
||||
use_pll: bool,
|
||||
pllsysclk: Option<u32>,
|
||||
pll48clk: Option<u32>,
|
||||
}
|
||||
|
||||
@ -31,6 +31,9 @@ pub struct Clocks {
|
||||
|
||||
#[cfg(any(rcc_h7))]
|
||||
pub apb4: Hertz,
|
||||
|
||||
#[cfg(rcc_f4)]
|
||||
pub pll48: Option<Hertz>,
|
||||
}
|
||||
|
||||
/// Frozen clock frequencies
|
||||
|
||||
34
examples/stm32f4/src/bin/hello.rs
Normal file
34
examples/stm32f4/src/bin/hello.rs
Normal file
@ -0,0 +1,34 @@
|
||||
#![no_std]
|
||||
#![no_main]
|
||||
#![feature(trait_alias)]
|
||||
#![feature(min_type_alias_impl_trait)]
|
||||
#![feature(impl_trait_in_bindings)]
|
||||
#![feature(type_alias_impl_trait)]
|
||||
#![allow(incomplete_features)]
|
||||
|
||||
use defmt::{info, panic};
|
||||
use embassy::executor::Spawner;
|
||||
use embassy::time::{Duration, Timer};
|
||||
use embassy_stm32::rcc::Config as RccConfig;
|
||||
use embassy_stm32::time::Hertz;
|
||||
use embassy_stm32::Config;
|
||||
use embassy_stm32::Peripherals;
|
||||
|
||||
#[path = "../example_common.rs"]
|
||||
mod example_common;
|
||||
|
||||
fn config() -> Config {
|
||||
let mut rcc_config = RccConfig::default();
|
||||
rcc_config.sys_ck = Some(Hertz(84_000_000));
|
||||
rcc_config.enable_debug_wfe = true;
|
||||
|
||||
Config::default().rcc(rcc_config)
|
||||
}
|
||||
|
||||
#[embassy::main(config = "config()")]
|
||||
async fn main(_spawner: Spawner, _p: Peripherals) -> ! {
|
||||
loop {
|
||||
info!("Hello World!");
|
||||
Timer::after(Duration::from_secs(1)).await;
|
||||
}
|
||||
}
|
||||
@ -1 +1 @@
|
||||
Subproject commit 62c8985228186a02a623d1acfb59b75a4865d303
|
||||
Subproject commit 0ad27b2fd1126c6c9d9f4602d1331f5d82f4aa26
|
||||
@ -1,5 +1,4 @@
|
||||
use chiptool::generate::CommonModule;
|
||||
use proc_macro2::TokenStream;
|
||||
use regex::Regex;
|
||||
use serde::Deserialize;
|
||||
use std::collections::{HashMap, HashSet};
|
||||
@ -10,7 +9,6 @@ use std::fs::File;
|
||||
use std::io::Write;
|
||||
use std::path::Path;
|
||||
use std::path::PathBuf;
|
||||
use std::str::FromStr;
|
||||
|
||||
use chiptool::util::ToSanitizedSnakeCase;
|
||||
use chiptool::{generate, ir, transform};
|
||||
@ -54,7 +52,7 @@ pub struct Peripheral {
|
||||
#[serde(default)]
|
||||
pub dma_channels: HashMap<String, Vec<PeripheralDmaChannel>>,
|
||||
#[serde(default)]
|
||||
pub interrupts: HashMap<String, String>
|
||||
pub interrupts: HashMap<String, String>,
|
||||
}
|
||||
|
||||
#[derive(Debug, Eq, PartialEq, Clone, Deserialize)]
|
||||
@ -353,8 +351,8 @@ pub fn gen(options: Options) {
|
||||
row.push(name.clone());
|
||||
row.push(bi.module.clone());
|
||||
row.push(bi.block.clone());
|
||||
row.push( signal.clone() );
|
||||
row.push( irq_name.to_ascii_uppercase() );
|
||||
row.push(signal.clone());
|
||||
row.push(irq_name.to_ascii_uppercase());
|
||||
interrupt_table.push(row)
|
||||
}
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user