first attempt at fixing the 2nd channel problem
This commit is contained in:
JuliDi
parent
915f79c974
commit
388d3e273d
@ -1,5 +1,7 @@
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#![macro_use]
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use core::marker::PhantomData;
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use embassy_hal_common::{into_ref, PeripheralRef};
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use crate::dma::{Transfer, TransferOptions};
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@ -108,166 +110,108 @@ pub enum ValueArray<'a> {
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Bit12Right(&'a [u16]),
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}
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pub struct Dac<'d, T: Instance, Tx> {
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ch1: bool,
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ch2: bool,
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txdma: PeripheralRef<'d, Tx>,
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_peri: PeripheralRef<'d, T>,
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}
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impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
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pub fn new_ch1(
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peri: impl Peripheral<P = T> + 'd,
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txdma: impl Peripheral<P = Tx> + 'd,
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_ch1: impl Peripheral<P = impl DacPin<T, 1>> + 'd,
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) -> Self {
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into_ref!(peri);
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Self::new_inner(peri, true, false, txdma)
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}
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pub fn new_ch2(
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peri: impl Peripheral<P = T> + 'd,
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txdma: impl Peripheral<P = Tx> + 'd,
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_ch2: impl Peripheral<P = impl DacPin<T, 2>> + 'd,
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) -> Self {
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into_ref!(peri);
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Self::new_inner(peri, false, true, txdma)
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}
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pub fn new_ch1_and_ch2(
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peri: impl Peripheral<P = T> + 'd,
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txdma: impl Peripheral<P = Tx> + 'd,
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_ch1: impl Peripheral<P = impl DacPin<T, 1>> + 'd,
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_ch2: impl Peripheral<P = impl DacPin<T, 2>> + 'd,
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) -> Self {
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into_ref!(peri);
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Self::new_inner(peri, true, true, txdma)
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}
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/// Perform initialisation steps for the DAC
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fn new_inner(peri: PeripheralRef<'d, T>, ch1: bool, ch2: bool, txdma: impl Peripheral<P = Tx> + 'd) -> Self {
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into_ref!(txdma);
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T::enable();
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T::reset();
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let mut dac = Self {
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ch1,
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ch2,
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txdma,
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_peri: peri,
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};
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// Configure each activated channel. All results can be `unwrap`ed since they
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// will only error if the channel is not configured (i.e. ch1, ch2 are false)
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if ch1 {
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dac.set_channel_mode(Channel::Ch1, 0).unwrap();
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dac.enable_channel(Channel::Ch1).unwrap();
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dac.set_trigger_enable(Channel::Ch1, true).unwrap();
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}
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if ch2 {
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dac.set_channel_mode(Channel::Ch2, 0).unwrap();
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dac.enable_channel(Channel::Ch2).unwrap();
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dac.set_trigger_enable(Channel::Ch2, true).unwrap();
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}
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dac
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}
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/// Check the channel is configured
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fn check_channel_configured(&self, ch: Channel) -> Result<(), Error> {
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if (ch == Channel::Ch1 && !self.ch1) || (ch == Channel::Ch2 && !self.ch2) {
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Err(Error::UnconfiguredChannel)
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} else {
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Ok(())
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}
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}
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pub trait DacChannel<T: Instance, Tx> {
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const CHANNEL: Channel;
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/// Enable trigger of the given channel
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fn set_trigger_enable(&mut self, ch: Channel, on: bool) -> Result<(), Error> {
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self.check_channel_configured(ch)?;
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fn set_trigger_enable(&mut self, on: bool) -> Result<(), Error> {
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T::regs().cr().modify(|reg| {
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reg.set_ten(ch.index(), on);
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reg.set_ten(Self::CHANNEL.index(), on);
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});
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Ok(())
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}
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/// Set mode register of the given channel
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fn set_channel_mode(&mut self, ch: Channel, val: u8) -> Result<(), Error> {
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self.check_channel_configured(ch)?;
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fn set_channel_mode(&mut self, val: u8) -> Result<(), Error> {
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T::regs().mcr().modify(|reg| {
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reg.set_mode(ch.index(), val);
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reg.set_mode(Self::CHANNEL.index(), val);
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});
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Ok(())
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}
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/// Set enable register of the given channel
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fn set_channel_enable(&mut self, ch: Channel, on: bool) -> Result<(), Error> {
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self.check_channel_configured(ch)?;
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fn set_channel_enable(&mut self, on: bool) -> Result<(), Error> {
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T::regs().cr().modify(|reg| {
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reg.set_en(ch.index(), on);
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reg.set_en(Self::CHANNEL.index(), on);
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});
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Ok(())
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}
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/// Enable the DAC channel `ch`
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pub fn enable_channel(&mut self, ch: Channel) -> Result<(), Error> {
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self.set_channel_enable(ch, true)
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fn enable_channel(&mut self) -> Result<(), Error> {
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self.set_channel_enable(true)
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}
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/// Disable the DAC channel `ch`
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pub fn disable_channel(&mut self, ch: Channel) -> Result<(), Error> {
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self.set_channel_enable(ch, false)
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}
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/// Select a new trigger for CH1 (disables the channel)
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pub fn select_trigger_ch1(&mut self, trigger: Ch1Trigger) -> Result<(), Error> {
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self.check_channel_configured(Channel::Ch1)?;
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unwrap!(self.disable_channel(Channel::Ch1));
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T::regs().cr().modify(|reg| {
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reg.set_tsel1(trigger.tsel());
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});
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Ok(())
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}
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/// Select a new trigger for CH2 (disables the channel)
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pub fn select_trigger_ch2(&mut self, trigger: Ch2Trigger) -> Result<(), Error> {
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self.check_channel_configured(Channel::Ch2)?;
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unwrap!(self.disable_channel(Channel::Ch2));
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T::regs().cr().modify(|reg| {
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reg.set_tsel2(trigger.tsel());
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});
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Ok(())
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fn disable_channel(&mut self) -> Result<(), Error> {
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self.set_channel_enable(false)
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}
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/// Perform a software trigger on `ch`
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pub fn trigger(&mut self, ch: Channel) -> Result<(), Error> {
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self.check_channel_configured(ch)?;
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fn trigger(&mut self) -> Result<(), Error> {
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T::regs().swtrigr().write(|reg| {
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reg.set_swtrig(ch.index(), true);
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reg.set_swtrig(Self::CHANNEL.index(), true);
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});
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Ok(())
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}
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/// Perform a software trigger on all channels
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pub fn trigger_all(&mut self) {
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T::regs().swtrigr().write(|reg| {
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reg.set_swtrig(Channel::Ch1.index(), true);
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reg.set_swtrig(Channel::Ch2.index(), true);
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});
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}
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/// Set a value to be output by the DAC on trigger.
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///
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/// The `value` is written to the corresponding "data holding register"
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pub fn set(&mut self, ch: Channel, value: Value) -> Result<(), Error> {
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self.check_channel_configured(ch)?;
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fn set(&mut self, value: Value) -> Result<(), Error> {
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match value {
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Value::Bit8(v) => T::regs().dhr8r(ch.index()).write(|reg| reg.set_dhr(v)),
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Value::Bit12Left(v) => T::regs().dhr12l(ch.index()).write(|reg| reg.set_dhr(v)),
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Value::Bit12Right(v) => T::regs().dhr12r(ch.index()).write(|reg| reg.set_dhr(v)),
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Value::Bit8(v) => T::regs().dhr8r(Self::CHANNEL.index()).write(|reg| reg.set_dhr(v)),
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Value::Bit12Left(v) => T::regs().dhr12l(Self::CHANNEL.index()).write(|reg| reg.set_dhr(v)),
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Value::Bit12Right(v) => T::regs().dhr12r(Self::CHANNEL.index()).write(|reg| reg.set_dhr(v)),
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}
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Ok(())
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}
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}
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pub struct Dac<'d, T: Instance, Tx> {
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ch1: DacCh1<'d, T, Tx>,
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ch2: DacCh2<'d, T, Tx>,
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}
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pub struct DacCh1<'d, T: Instance, Tx> {
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_peri: PeripheralRef<'d, T>,
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dma: PeripheralRef<'d, Tx>,
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}
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pub struct DacCh2<'d, T: Instance, Tx> {
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phantom: PhantomData<&'d mut T>,
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dma: PeripheralRef<'d, Tx>,
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}
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impl<'d, T: Instance, Tx> DacCh1<'d, T, Tx> {
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/// Perform initialisation steps for the DAC
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pub fn new(
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peri: impl Peripheral<P = T> + 'd,
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dma: impl Peripheral<P = Tx> + 'd,
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_pin: impl Peripheral<P = impl DacPin<T, 1>> + 'd,
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) -> Self {
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into_ref!(peri, dma);
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T::enable();
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T::reset();
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let mut dac = Self { _peri: peri, dma };
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// Configure each activated channel. All results can be `unwrap`ed since they
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// will only error if the channel is not configured (i.e. ch1, ch2 are false)
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dac.set_channel_mode(0).unwrap();
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dac.enable_channel().unwrap();
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dac.set_trigger_enable(true).unwrap();
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dac
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}
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/// Select a new trigger for CH1 (disables the channel)
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pub fn select_trigger(&mut self, trigger: Ch1Trigger) -> Result<(), Error> {
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unwrap!(self.disable_channel());
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T::regs().cr().modify(|reg| {
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reg.set_tsel1(trigger.tsel());
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});
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Ok(())
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}
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/// Write `data` to the DAC CH1 via DMA.
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///
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@ -276,36 +220,12 @@ impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
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/// Note that for performance reasons in circular mode the transfer complete interrupt is disabled.
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///
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/// **Important:** Channel 1 has to be configured for the DAC instance!
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pub async fn write_ch1(&mut self, data: ValueArray<'_>, circular: bool) -> Result<(), Error>
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async fn write(&mut self, data: ValueArray<'_>, circular: bool) -> Result<(), Error>
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where
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Tx: Dma<T>,
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{
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self.check_channel_configured(Channel::Ch1)?;
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self.write_inner(data, circular, Channel::Ch1).await
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}
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/// Write `data` to the DAC CH2 via DMA.
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///
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/// To prevent delays/glitches when outputting a periodic waveform, the `circular` flag can be set.
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/// This will configure a circular DMA transfer that periodically outputs the `data`.
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/// Note that for performance reasons in circular mode the transfer complete interrupt is disabled.
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///
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/// **Important:** Channel 2 has to be configured for the DAC instance!
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pub async fn write_ch2(&mut self, data: ValueArray<'_>, circular: bool) -> Result<(), Error>
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where
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Tx: Dma<T>,
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{
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self.check_channel_configured(Channel::Ch2)?;
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self.write_inner(data, circular, Channel::Ch2).await
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}
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/// Performs the dma write for the given channel.
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/// TODO: Should self be &mut?
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async fn write_inner(&self, data_ch1: ValueArray<'_>, circular: bool, channel: Channel) -> Result<(), Error>
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where
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Tx: Dma<T>,
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{
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let channel = channel.index();
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let channel = Channel::Ch1.index();
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debug!("Writing to channel {}", channel);
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// Enable DAC and DMA
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T::regs().cr().modify(|w| {
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@ -313,11 +233,11 @@ impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
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w.set_dmaen(channel, true);
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});
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let tx_request = self.txdma.request();
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let dma_channel = &self.txdma;
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let tx_request = self.dma.request();
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let dma_channel = &self.dma;
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// Initiate the correct type of DMA transfer depending on what data is passed
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let tx_f = match data_ch1 {
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let tx_f = match data {
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ValueArray::Bit8(buf) => unsafe {
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Transfer::new_write(
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dma_channel,
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@ -374,6 +294,168 @@ impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
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}
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}
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impl<'d, T: Instance, Tx> DacCh2<'d, T, Tx> {
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/// Perform initialisation steps for the DAC
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pub fn new_ch2(
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peri: impl Peripheral<P = T> + 'd,
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dma: impl Peripheral<P = Tx> + 'd,
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_pin: impl Peripheral<P = impl DacPin<T, 2>> + 'd,
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) -> Self {
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into_ref!(peri, dma);
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T::enable();
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T::reset();
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let mut dac = Self {
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phantom: PhantomData,
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dma,
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};
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// Configure each activated channel. All results can be `unwrap`ed since they
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// will only error if the channel is not configured (i.e. ch1, ch2 are false)
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dac.set_channel_mode(0).unwrap();
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dac.enable_channel().unwrap();
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dac.set_trigger_enable(true).unwrap();
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dac
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}
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/// Select a new trigger for CH1 (disables the channel)
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pub fn select_trigger(&mut self, trigger: Ch2Trigger) -> Result<(), Error> {
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unwrap!(self.disable_channel());
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T::regs().cr().modify(|reg| {
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reg.set_tsel2(trigger.tsel());
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});
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Ok(())
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}
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/// Write `data` to the DAC CH1 via DMA.
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///
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/// To prevent delays/glitches when outputting a periodic waveform, the `circular` flag can be set.
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/// This will configure a circular DMA transfer that periodically outputs the `data`.
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/// Note that for performance reasons in circular mode the transfer complete interrupt is disabled.
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///
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/// **Important:** Channel 1 has to be configured for the DAC instance!
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async fn write(&mut self, data: ValueArray<'_>, circular: bool) -> Result<(), Error>
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where
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Tx: Dma<T>,
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{
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let channel = Channel::Ch2.index();
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debug!("Writing to channel {}", channel);
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// Enable DAC and DMA
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T::regs().cr().modify(|w| {
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w.set_en(channel, true);
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w.set_dmaen(channel, true);
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});
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let tx_request = self.dma.request();
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let dma_channel = &self.dma;
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// Initiate the correct type of DMA transfer depending on what data is passed
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let tx_f = match data {
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ValueArray::Bit8(buf) => unsafe {
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Transfer::new_write(
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dma_channel,
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tx_request,
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buf,
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T::regs().dhr8r(channel).as_ptr() as *mut u8,
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TransferOptions {
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circular,
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half_transfer_ir: false,
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complete_transfer_ir: !circular,
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},
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)
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},
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ValueArray::Bit12Left(buf) => unsafe {
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Transfer::new_write(
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dma_channel,
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tx_request,
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buf,
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T::regs().dhr12l(channel).as_ptr() as *mut u16,
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TransferOptions {
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circular,
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half_transfer_ir: false,
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complete_transfer_ir: !circular,
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},
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)
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},
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ValueArray::Bit12Right(buf) => unsafe {
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Transfer::new_write(
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dma_channel,
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tx_request,
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buf,
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T::regs().dhr12r(channel).as_ptr() as *mut u16,
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TransferOptions {
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circular,
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half_transfer_ir: false,
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complete_transfer_ir: !circular,
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},
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)
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},
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};
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tx_f.await;
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// finish dma
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// TODO: Do we need to check any status registers here?
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T::regs().cr().modify(|w| {
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// Disable the DAC peripheral
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w.set_en(channel, false);
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// Disable the DMA. TODO: Is this necessary?
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w.set_dmaen(channel, false);
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});
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Ok(())
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}
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}
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impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
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pub fn new(
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peri: impl Peripheral<P = T> + 'd,
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dma_ch1: impl Peripheral<P = Tx> + 'd,
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dma_ch2: impl Peripheral<P = Tx> + 'd,
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_pin_ch1: impl Peripheral<P = impl DacPin<T, 1>> + 'd,
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_pin_ch2: impl Peripheral<P = impl DacPin<T, 2>> + 'd,
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) -> Self {
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into_ref!(peri, dma_ch1, dma_ch2);
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T::enable();
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T::reset();
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let mut dac_ch1 = DacCh1 {
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_peri: peri,
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dma: dma_ch1,
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};
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let mut dac_ch2 = DacCh2 {
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phantom: PhantomData,
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dma: dma_ch2,
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};
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// Configure each activated channel. All results can be `unwrap`ed since they
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// will only error if the channel is not configured (i.e. ch1, ch2 are false)
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dac_ch1.set_channel_mode(0).unwrap();
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dac_ch1.enable_channel().unwrap();
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dac_ch1.set_trigger_enable(true).unwrap();
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dac_ch1.set_channel_mode(0).unwrap();
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dac_ch1.enable_channel().unwrap();
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dac_ch1.set_trigger_enable(true).unwrap();
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Self {
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ch1: dac_ch1,
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ch2: dac_ch2,
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}
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}
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}
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||||
|
||||
impl<'d, T: Instance, Tx> DacChannel<T, Tx> for DacCh1<'d, T, Tx> {
|
||||
const CHANNEL: Channel = Channel::Ch1;
|
||||
}
|
||||
|
||||
impl<'d, T: Instance, Tx> DacChannel<T, Tx> for DacCh2<'d, T, Tx> {
|
||||
const CHANNEL: Channel = Channel::Ch2;
|
||||
}
|
||||
|
||||
pub(crate) mod sealed {
|
||||
pub trait Instance {
|
||||
fn regs() -> &'static crate::pac::dac::Dac;
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user