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partial alternate function configuration on STM32f1

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This commit is contained in:
Tobias Pisani
2021-10-09 11:35:05 +02:00
parent f9a576d13d
commit 39880de958
9 changed files with 72 additions and 28 deletions
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4
embassy-stm32/src/eth/v2/mod.rs
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@ -10,7 +10,7 @@ use embassy_net::{Device, DeviceCapabilities, LinkState, PacketBuf, MTU};
use crate::gpio::sealed::Pin as __GpioPin;
use crate::gpio::Pin as GpioPin;
use crate::gpio::{sealed::OutputType::PushPull, AnyPin};
use crate::gpio::{sealed::AFType::OutputPushPull, AnyPin};
use crate::pac::gpio::vals::Ospeedr;
use crate::pac::{ETH, RCC, SYSCFG};
use crate::peripherals;
@ -416,7 +416,7 @@ macro_rules! impl_pin {
fn configure(&mut self) {
// NOTE(unsafe) Exclusive access to the registers
critical_section::with(|_| unsafe {
self.set_as_af($af, PushPull);
self.set_as_af($af, OutputPushPull);
self.block()
.ospeedr()
.modify(|w| w.set_ospeedr(self.pin() as usize, Ospeedr::VERYHIGHSPEED));