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Update stm32-data

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This commit is contained in:
Dario Nieuwenhuis
2022-02-14 02:12:06 +01:00
parent c8f9f1bead
commit 39d06b59cd
13 changed files with 56 additions and 102 deletions
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52
embassy-stm32/src/i2c/v1.rs
View File

@ -108,11 +108,11 @@ impl<'d, T: Instance> I2c<'d, T> {
// Send a START condition
T::regs().cr1().modify(|reg| {
reg.set_start(i2c::vals::Start::START);
reg.set_start(true);
});
// Wait until START condition was generated
while self.check_and_clear_error_flags()?.sb() == i2c::vals::Sb::NOSTART {}
while !self.check_and_clear_error_flags()?.start() {}
// Also wait until signalled we're master and everything is waiting for us
while {
@ -126,13 +126,9 @@ impl<'d, T: Instance> I2c<'d, T> {
T::regs().dr().write(|reg| reg.set_dr(addr << 1));
// Wait until address was sent
while {
// Check for any I2C errors. If a NACK occurs, the ADDR bit will never be set.
let sr1 = self.check_and_clear_error_flags()?;
// Wait for the address to be acknowledged
!sr1.addr()
} {}
// Wait for the address to be acknowledged
// Check for any I2C errors. If a NACK occurs, the ADDR bit will never be set.
while !self.check_and_clear_error_flags()?.addr() {}
// Clear condition by reading SR2
let _ = T::regs().sr2().read();
@ -150,7 +146,7 @@ impl<'d, T: Instance> I2c<'d, T> {
// Wait until we're ready for sending
while {
// Check for any I2C errors. If a NACK occurs, the ADDR bit will never be set.
!self.check_and_clear_error_flags()?.tx_e()
!self.check_and_clear_error_flags()?.txe()
} {}
// Push out a byte of data
@ -170,7 +166,7 @@ impl<'d, T: Instance> I2c<'d, T> {
// Check for any potential error conditions.
self.check_and_clear_error_flags()?;
!T::regs().sr1().read().rx_ne()
!T::regs().sr1().read().rxne()
} {}
let value = T::regs().dr().read().dr();
@ -182,13 +178,13 @@ impl<'d, T: Instance> I2c<'d, T> {
// Send a START condition and set ACK bit
unsafe {
T::regs().cr1().modify(|reg| {
reg.set_start(i2c::vals::Start::START);
reg.set_start(true);
reg.set_ack(true);
});
}
// Wait until START condition was generated
while unsafe { T::regs().sr1().read().sb() } == i2c::vals::Sb::NOSTART {}
while unsafe { !T::regs().sr1().read().start() } {}
// Also wait until signalled we're master and everything is waiting for us
while {
@ -197,24 +193,14 @@ impl<'d, T: Instance> I2c<'d, T> {
} {}
// Set up current address, we're trying to talk to
unsafe {
T::regs().dr().write(|reg| reg.set_dr((addr << 1) + 1));
}
unsafe { T::regs().dr().write(|reg| reg.set_dr((addr << 1) + 1)) }
// Wait until address was sent
while {
unsafe {
let sr1 = self.check_and_clear_error_flags()?;
// Wait for the address to be acknowledged
!sr1.addr()
}
} {}
// Wait for the address to be acknowledged
while unsafe { !self.check_and_clear_error_flags()?.addr() } {}
// Clear condition by reading SR2
unsafe {
let _ = T::regs().sr2().read();
}
let _ = unsafe { T::regs().sr2().read() };
// Receive bytes into buffer
for c in buffer {
@ -225,15 +211,15 @@ impl<'d, T: Instance> I2c<'d, T> {
unsafe {
T::regs().cr1().modify(|reg| {
reg.set_ack(false);
reg.set_stop(i2c::vals::Stop::STOP);
});
reg.set_stop(true);
})
}
// Receive last byte
*last = unsafe { self.recv_byte()? };
// Wait for the STOP to be sent.
while unsafe { T::regs().cr1().read().stop() == i2c::vals::Stop::STOP } {}
while unsafe { T::regs().cr1().read().stop() } {}
// Fallthrough is success
Ok(())
@ -246,11 +232,9 @@ impl<'d, T: Instance> I2c<'d, T> {
unsafe {
self.write_bytes(addr, bytes)?;
// Send a STOP condition
T::regs()
.cr1()
.modify(|reg| reg.set_stop(i2c::vals::Stop::STOP));
T::regs().cr1().modify(|reg| reg.set_stop(true));
// Wait for STOP condition to transmit.
while T::regs().cr1().read().stop() == i2c::vals::Stop::STOP {}
while T::regs().cr1().read().stop() {}
};
// Fallthrough is success

18
embassy-stm32/src/i2c/v2.rs
View File

@ -132,7 +132,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
fn master_stop(&mut self) {
unsafe {
T::regs().cr2().write(|w| w.set_stop(i2c::vals::Stop::STOP));
T::regs().cr2().write(|w| w.set_stop(true));
}
}
@ -143,7 +143,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
// Wait for any previous address sequence to end
// automatically. This could be up to 50% of a bus
// cycle (ie. up to 0.5/freq)
while T::regs().cr2().read().start() == i2c::vals::Start::START {}
while T::regs().cr2().read().start() {}
}
// Set START and prepare to receive bytes into
@ -158,10 +158,10 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
T::regs().cr2().modify(|w| {
w.set_sadd((address << 1 | 0) as u16);
w.set_add10(i2c::vals::Add::BIT7);
w.set_rd_wrn(i2c::vals::RdWrn::READ);
w.set_add10(i2c::vals::Addmode::BIT7);
w.set_dir(i2c::vals::Dir::READ);
w.set_nbytes(length as u8);
w.set_start(i2c::vals::Start::START);
w.set_start(true);
w.set_autoend(stop.autoend());
w.set_reload(reload);
});
@ -173,7 +173,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
// Wait for any previous address sequence to end
// automatically. This could be up to 50% of a bus
// cycle (ie. up to 0.5/freq)
while T::regs().cr2().read().start() == i2c::vals::Start::START {}
while T::regs().cr2().read().start() {}
let reload = if reload {
i2c::vals::Reload::NOTCOMPLETED
@ -186,10 +186,10 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
// I2C is in slave mode.
T::regs().cr2().modify(|w| {
w.set_sadd((address << 1 | 0) as u16);
w.set_add10(i2c::vals::Add::BIT7);
w.set_rd_wrn(i2c::vals::RdWrn::WRITE);
w.set_add10(i2c::vals::Addmode::BIT7);
w.set_dir(i2c::vals::Dir::WRITE);
w.set_nbytes(length as u8);
w.set_start(i2c::vals::Start::START);
w.set_start(true);
w.set_autoend(stop.autoend());
w.set_reload(reload);
});