Update stm32-data
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@ -132,7 +132,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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fn master_stop(&mut self) {
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unsafe {
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T::regs().cr2().write(|w| w.set_stop(i2c::vals::Stop::STOP));
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T::regs().cr2().write(|w| w.set_stop(true));
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}
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}
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@ -143,7 +143,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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// Wait for any previous address sequence to end
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// automatically. This could be up to 50% of a bus
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// cycle (ie. up to 0.5/freq)
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while T::regs().cr2().read().start() == i2c::vals::Start::START {}
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while T::regs().cr2().read().start() {}
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}
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// Set START and prepare to receive bytes into
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@ -158,10 +158,10 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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T::regs().cr2().modify(|w| {
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w.set_sadd((address << 1 | 0) as u16);
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w.set_add10(i2c::vals::Add::BIT7);
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w.set_rd_wrn(i2c::vals::RdWrn::READ);
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w.set_add10(i2c::vals::Addmode::BIT7);
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w.set_dir(i2c::vals::Dir::READ);
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w.set_nbytes(length as u8);
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w.set_start(i2c::vals::Start::START);
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w.set_start(true);
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w.set_autoend(stop.autoend());
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w.set_reload(reload);
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});
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@ -173,7 +173,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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// Wait for any previous address sequence to end
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// automatically. This could be up to 50% of a bus
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// cycle (ie. up to 0.5/freq)
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while T::regs().cr2().read().start() == i2c::vals::Start::START {}
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while T::regs().cr2().read().start() {}
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let reload = if reload {
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i2c::vals::Reload::NOTCOMPLETED
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@ -186,10 +186,10 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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// I2C is in slave mode.
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T::regs().cr2().modify(|w| {
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w.set_sadd((address << 1 | 0) as u16);
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w.set_add10(i2c::vals::Add::BIT7);
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w.set_rd_wrn(i2c::vals::RdWrn::WRITE);
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w.set_add10(i2c::vals::Addmode::BIT7);
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w.set_dir(i2c::vals::Dir::WRITE);
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w.set_nbytes(length as u8);
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w.set_start(i2c::vals::Start::START);
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w.set_start(true);
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w.set_autoend(stop.autoend());
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w.set_reload(reload);
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});
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