Update stm32-data
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@ -1,5 +1,5 @@
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use crate::pac::flash::vals::Latency;
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use crate::pac::rcc::vals::{Hpre, Hsebyp, Pllmul, Pllsrc, Ppre, Prediv, Sw, Usbpre};
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use crate::pac::rcc::vals::{Hpre, Pllmul, Pllsrc, Ppre, Prediv, Sw, Usbpre};
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use crate::pac::{FLASH, RCC};
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use crate::rcc::{set_freqs, Clocks};
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use crate::time::Hertz;
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@ -106,11 +106,7 @@ pub(crate) unsafe fn init(config: Config) {
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// Enable HSE
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if config.hse.is_some() {
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RCC.cr().write(|w| {
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w.set_hsebyp(if config.bypass_hse {
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Hsebyp::BYPASSED
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} else {
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Hsebyp::NOTBYPASSED
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});
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w.set_hsebyp(config.bypass_hse);
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// We turn on clock security to switch to HSI when HSE fails
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w.set_csson(true);
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w.set_hseon(true);
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@ -164,7 +160,7 @@ pub(crate) unsafe fn init(config: Config) {
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apb2: Hertz(pclk2),
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apb1_tim: Hertz(pclk1 * timer_mul1),
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apb2_tim: Hertz(pclk2 * timer_mul2),
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ahb: Hertz(hclk),
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ahb1: Hertz(hclk),
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});
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}
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