Enable RTC on STM32WL chips (#1645)
* Add clippy allow to not report if same then branch * Support enabling RTC clock on STM32WL * Add clippy allow to not report if same then branch * Support enabling RTC clock on STM32WL * Add rtc example for stm32wl * Address code review feedback
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@ -1,4 +1,5 @@
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use crate::pac::{FLASH, RCC};
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use crate::pac::pwr::vals::Dbp;
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use crate::pac::{FLASH, PWR, RCC};
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use crate::rcc::{set_freqs, Clocks};
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use crate::time::Hertz;
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@ -184,6 +185,8 @@ pub struct Config {
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pub apb1_pre: APBPrescaler,
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pub apb2_pre: APBPrescaler,
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pub enable_lsi: bool,
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pub enable_rtc_apb: bool,
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pub rtc_mux: RtcClockSource,
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}
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impl Default for Config {
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@ -196,10 +199,25 @@ impl Default for Config {
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apb1_pre: APBPrescaler::NotDivided,
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apb2_pre: APBPrescaler::NotDivided,
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enable_lsi: false,
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enable_rtc_apb: false,
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rtc_mux: RtcClockSource::LSI32,
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}
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}
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}
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pub enum RtcClockSource {
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LSE32,
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LSI32,
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}
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#[repr(u8)]
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pub enum Lsedrv {
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Low = 0,
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MediumLow = 1,
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MediumHigh = 2,
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High = 3,
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}
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pub(crate) unsafe fn init(config: Config) {
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let (sys_clk, sw, vos) = match config.mux {
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ClockSrc::HSI16 => (HSI_FREQ.0, 0x01, VoltageScale::Range2),
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@ -266,6 +284,32 @@ pub(crate) unsafe fn init(config: Config) {
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while FLASH.acr().read().latency() != ws {}
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match config.rtc_mux {
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RtcClockSource::LSE32 => {
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// 1. Unlock the backup domain
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PWR.cr1().modify(|w| w.set_dbp(Dbp::ENABLED));
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// 2. Setup the LSE
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RCC.bdcr().modify(|w| {
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// Enable LSE
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w.set_lseon(true);
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// Max drive strength
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// TODO: should probably be settable
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w.set_lsedrv(Lsedrv::High as u8); //---// PAM - should not be commented
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});
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// Wait until LSE is running
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while !RCC.bdcr().read().lserdy() {}
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}
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RtcClockSource::LSI32 => {
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// Turn on the internal 32 kHz LSI oscillator
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RCC.csr().modify(|w| w.set_lsion(true));
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// Wait until LSI is running
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while !RCC.csr().read().lsirdy() {}
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}
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}
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match config.mux {
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ClockSrc::HSI16 => {
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// Enable HSI16
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@ -287,11 +331,26 @@ pub(crate) unsafe fn init(config: Config) {
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w.set_msirgsel(true);
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w.set_msirange(range.into());
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w.set_msion(true);
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if let RtcClockSource::LSE32 = config.rtc_mux {
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// If LSE is enabled, enable calibration of MSI
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w.set_msipllen(true);
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} else {
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w.set_msipllen(false);
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}
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});
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while !RCC.cr().read().msirdy() {}
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}
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}
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if config.enable_rtc_apb {
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// enable peripheral clock for communication
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crate::pac::RCC.apb1enr1().modify(|w| w.set_rtcapben(true));
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// read to allow the pwr clock to enable
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crate::pac::PWR.cr1().read();
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}
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RCC.extcfgr().modify(|w| {
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if config.shd_ahb_pre == AHBPrescaler::NotDivided {
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w.set_shdhpre(0);
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@ -172,6 +172,7 @@ impl sealed::Instance for crate::peripherals::RTC {
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const BACKUP_REGISTER_COUNT: usize = 32;
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fn read_backup_register(_rtc: &Rtc, register: usize) -> Option<u32> {
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#[allow(clippy::if_same_then_else)]
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if register < Self::BACKUP_REGISTER_COUNT {
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//Some(rtc.bkpr()[register].read().bits())
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None // RTC3 backup registers come from the TAMP peripe=heral, not RTC. Not() even in the L412 PAC
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@ -3,7 +3,7 @@
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runner = "probe-rs run --chip STM32WLE5JCIx"
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[build]
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target = "thumbv7em-none-eabihf"
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target = "thumbv7em-none-eabi"
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[env]
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DEFMT_LOG = "trace"
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@ -8,7 +8,7 @@ license = "MIT OR Apache-2.0"
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embassy-sync = { version = "0.2.0", path = "../../embassy-sync", features = ["defmt"] }
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embassy-executor = { version = "0.2.0", path = "../../embassy-executor", features = ["nightly", "arch-cortex-m", "executor-thread", "defmt", "integrated-timers"] }
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embassy-time = { version = "0.1.2", path = "../../embassy-time", features = ["nightly", "unstable-traits", "defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
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embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["nightly", "unstable-traits", "defmt", "stm32wl55jc-cm4", "time-driver-any", "memory-x", "unstable-pac", "exti"] }
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embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["nightly", "unstable-traits", "defmt", "stm32wl55jc-cm4", "time-driver-any", "memory-x", "unstable-pac", "exti", "chrono"] }
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embassy-embedded-hal = { version = "0.1.0", path = "../../embassy-embedded-hal" }
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embassy-lora = { version = "0.1.0", path = "../../embassy-lora", features = ["stm32wl", "time", "defmt"] }
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lora-phy = { version = "1" }
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@ -25,6 +25,7 @@ embedded-storage = "0.3.0"
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panic-probe = { version = "0.3", features = ["print-defmt"] }
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futures = { version = "0.3.17", default-features = false, features = ["async-await"] }
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heapless = { version = "0.7.5", default-features = false }
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chrono = { version = "^0.4", default-features = false }
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[patch.crates-io]
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lora-phy = { git = "https://github.com/embassy-rs/lora-phy", rev = "ad289428fd44b02788e2fa2116445cc8f640a265" }
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43
examples/stm32wl/src/bin/rtc.rs
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43
examples/stm32wl/src/bin/rtc.rs
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@ -0,0 +1,43 @@
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#![no_std]
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#![no_main]
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#![feature(type_alias_impl_trait)]
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use chrono::{NaiveDate, NaiveDateTime};
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use defmt::*;
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use embassy_executor::Spawner;
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use embassy_stm32::rcc::{self, ClockSrc};
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use embassy_stm32::rtc::{Rtc, RtcConfig};
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use embassy_stm32::Config;
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use embassy_time::{Duration, Timer};
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use {defmt_rtt as _, panic_probe as _};
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#[embassy_executor::main]
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async fn main(_spawner: Spawner) {
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let p = {
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let mut config = Config::default();
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config.rcc.mux = ClockSrc::HSE32;
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config.rcc.rtc_mux = rcc::RtcClockSource::LSE32;
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config.rcc.enable_rtc_apb = true;
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embassy_stm32::init(config)
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};
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info!("Hello World!");
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let now = NaiveDate::from_ymd_opt(2020, 5, 15)
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.unwrap()
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.and_hms_opt(10, 30, 15)
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.unwrap();
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let mut rtc = Rtc::new(
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p.RTC,
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RtcConfig::default().clock_config(embassy_stm32::rtc::RtcClockSource::LSE),
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);
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info!("Got RTC! {:?}", now.timestamp());
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rtc.set_datetime(now.into()).expect("datetime not set");
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// In reality the delay would be much longer
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Timer::after(Duration::from_millis(20000)).await;
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let then: NaiveDateTime = rtc.now().unwrap().into();
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info!("Got RTC! {:?}", then.timestamp());
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}
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