Merge pull request #2015 from willglynn/stm32u5_faster_clocks
stm32: u5: implement >55 MHz clock speeds
This commit is contained in:
Dario Nieuwenhuis
GitHub
commit
3bf8e4de5f
@ -1,7 +1,7 @@
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use stm32_metapac::rcc::vals::{Msirange, Msirgsel, Pllm, Pllsrc, Sw};
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use stm32_metapac::rcc::vals::{Msirange, Msirgsel, Pllm, Pllmboost, Pllrge, Pllsrc, Sw};
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pub use super::bus::{AHBPrescaler, APBPrescaler};
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use crate::pac::{FLASH, RCC};
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use crate::pac::{FLASH, PWR, RCC};
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use crate::rcc::{set_freqs, Clocks};
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use crate::time::Hertz;
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@ -15,23 +15,86 @@ pub use crate::pac::pwr::vals::Vos as VoltageScale;
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#[derive(Copy, Clone)]
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pub enum ClockSrc {
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/// Use an internal medium speed oscillator (MSIS) as the system clock.
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MSI(MSIRange),
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/// Use the external high speed clock as the system clock.
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///
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/// HSE clocks faster than 25 MHz require at least `VoltageScale::RANGE3`, and HSE clocks must
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/// never exceed 50 MHz.
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HSE(Hertz),
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/// Use the 16 MHz internal high speed oscillator as the system clock.
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HSI16,
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PLL1R(PllSrc, PllM, PllN, PllClkDiv),
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/// Use PLL1 as the system clock.
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PLL1R(PllConfig),
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}
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impl Default for ClockSrc {
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fn default() -> Self {
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// The default system clock source is MSIS @ 4 MHz, per RM0456 § 11.4.9
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ClockSrc::MSI(MSIRange::Range4mhz)
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}
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}
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#[derive(Clone, Copy, Debug)]
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pub struct PllConfig {
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/// The clock source for the PLL.
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pub source: PllSrc,
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/// The PLL prescaler.
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///
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/// The clock speed of the `source` divided by `m` must be between 4 and 16 MHz.
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pub m: PllM,
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/// The PLL multiplier.
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///
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/// The multiplied clock – `source` divided by `m` times `n` – must be between 128 and 544
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/// MHz. The upper limit may be lower depending on the `Config { voltage_range }`.
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pub n: PllN,
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/// The divider for the R output.
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///
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/// When used to drive the system clock, `source` divided by `m` times `n` divided by `r`
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/// must not exceed 160 MHz. System clocks above 55 MHz require a non-default
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/// `Config { voltage_range }`.
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pub r: PllClkDiv,
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}
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impl PllConfig {
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/// A configuration for HSI16 / 1 * 10 / 1 = 160 MHz
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pub const fn hsi16_160mhz() -> Self {
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PllConfig {
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source: PllSrc::HSI16,
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m: PllM::NotDivided,
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n: PllN::Mul10,
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r: PllClkDiv::NotDivided,
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}
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}
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/// A configuration for MSIS @ 48 MHz / 3 * 10 / 1 = 160 MHz
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pub const fn msis_160mhz() -> Self {
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PllConfig {
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source: PllSrc::MSIS(MSIRange::Range48mhz),
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m: PllM::Div3,
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n: PllN::Mul10,
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r: PllClkDiv::NotDivided,
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}
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}
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}
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#[derive(Clone, Copy, Debug)]
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pub enum PllSrc {
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MSI(MSIRange),
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/// Use an internal medium speed oscillator as the PLL source.
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MSIS(MSIRange),
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/// Use the external high speed clock as the system PLL source.
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///
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/// HSE clocks faster than 25 MHz require at least `VoltageScale::RANGE3`, and HSE clocks must
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/// never exceed 50 MHz.
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HSE(Hertz),
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/// Use the 16 MHz internal high speed oscillator as the PLL source.
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HSI16,
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}
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impl Into<Pllsrc> for PllSrc {
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fn into(self) -> Pllsrc {
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match self {
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PllSrc::MSI(..) => Pllsrc::MSIS,
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PllSrc::MSIS(..) => Pllsrc::MSIS,
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PllSrc::HSE(..) => Pllsrc::HSE,
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PllSrc::HSI16 => Pllsrc::HSI16,
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}
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@ -41,57 +104,45 @@ impl Into<Pllsrc> for PllSrc {
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seq_macro::seq!(N in 2..=128 {
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#[derive(Copy, Clone, Debug)]
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pub enum PllClkDiv {
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NotDivided,
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NotDivided = 1,
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#(
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Div~N = (N-1),
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Div~N = N,
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)*
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}
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impl PllClkDiv {
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fn to_div(&self) -> u8 {
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match self {
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PllClkDiv::NotDivided => 1,
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PllClkDiv::NotDivided => 0,
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#(
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PllClkDiv::Div~N => N + 1,
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PllClkDiv::Div~N => N - 1,
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)*
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}
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}
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}
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});
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impl Into<u8> for PllClkDiv {
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fn into(self) -> u8 {
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(self as u8) + 1
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}
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}
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seq_macro::seq!(N in 4..=512 {
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#[derive(Copy, Clone, Debug)]
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pub enum PllN {
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NotMultiplied,
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NotMultiplied = 1,
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#(
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Mul~N = N-1,
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Mul~N = N,
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)*
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}
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impl PllN {
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fn to_mul(&self) -> u16 {
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match self {
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PllN::NotMultiplied => 1,
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PllN::NotMultiplied => 0,
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#(
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PllN::Mul~N => N + 1,
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PllN::Mul~N => N - 1,
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)*
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}
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}
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}
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});
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impl Into<u16> for PllN {
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fn into(self) -> u16 {
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(self as u16) + 1
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}
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}
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// Pre-division
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#[derive(Copy, Clone, Debug)]
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pub enum PllM {
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@ -132,6 +183,7 @@ impl Into<Sw> for ClockSrc {
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#[derive(Debug, Copy, Clone)]
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pub enum MSIRange {
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/// The 48 MHz MSI speed is unavailable in `VoltageScale::RANGE4`.
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Range48mhz = 48_000_000,
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Range24mhz = 24_000_000,
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Range16mhz = 16_000_000,
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@ -179,12 +231,6 @@ impl Into<Msirange> for MSIRange {
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}
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}
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impl Default for MSIRange {
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fn default() -> Self {
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MSIRange::Range4mhz
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}
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}
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#[derive(Copy, Clone)]
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pub struct Config {
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pub mux: ClockSrc,
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@ -193,24 +239,57 @@ pub struct Config {
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pub apb2_pre: APBPrescaler,
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pub apb3_pre: APBPrescaler,
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pub hsi48: bool,
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/// The voltage range influences the maximum clock frequencies for different parts of the
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/// device. In particular, system clocks exceeding 110 MHz require `RANGE1`, and system clocks
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/// exceeding 55 MHz require at least `RANGE2`.
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///
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/// See RM0456 § 10.5.4 for a general overview and § 11.4.10 for clock source frequency limits.
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pub voltage_range: VoltageScale,
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}
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impl Default for Config {
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fn default() -> Self {
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Self {
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mux: ClockSrc::MSI(MSIRange::default()),
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ahb_pre: AHBPrescaler::DIV1,
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apb1_pre: APBPrescaler::DIV1,
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apb2_pre: APBPrescaler::DIV1,
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apb3_pre: APBPrescaler::DIV1,
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hsi48: false,
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}
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}
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}
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impl Config {
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unsafe fn init_hsi16(&self) -> Hertz {
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RCC.cr().write(|w| w.set_hsion(true));
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while !RCC.cr().read().hsirdy() {}
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HSI_FREQ
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}
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unsafe fn init_hse(&self, frequency: Hertz) -> Hertz {
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// Check frequency limits per RM456 § 11.4.10
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match self.voltage_range {
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VoltageScale::RANGE1 | VoltageScale::RANGE2 | VoltageScale::RANGE3 => {
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assert!(frequency.0 <= 50_000_000);
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}
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VoltageScale::RANGE4 => {
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assert!(frequency.0 <= 25_000_000);
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}
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}
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// Enable HSE, and wait for it to stabilize
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RCC.cr().write(|w| w.set_hseon(true));
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while !RCC.cr().read().hserdy() {}
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frequency
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}
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unsafe fn init_msis(&self, range: MSIRange) -> Hertz {
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// Check MSI output per RM0456 § 11.4.10
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match self.voltage_range {
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VoltageScale::RANGE4 => {
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assert!(range as u32 <= 24_000_000);
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}
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_ => {}
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}
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// RM0456 § 11.8.2: spin until MSIS is off or MSIS is ready before setting its range
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loop {
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let cr = RCC.cr().read();
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if cr.msison() == false || cr.msisrdy() == true {
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break;
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}
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}
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pub(crate) unsafe fn init(config: Config) {
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let sys_clk = match config.mux {
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ClockSrc::MSI(range) => {
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RCC.icscr1().modify(|w| {
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let bits: Msirange = range.into();
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w.set_msisrange(bits);
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@ -221,75 +300,159 @@ pub(crate) unsafe fn init(config: Config) {
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w.set_msison(true);
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});
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while !RCC.cr().read().msisrdy() {}
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Hertz(range as u32)
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}
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}
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range.into()
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impl Default for Config {
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fn default() -> Self {
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Self {
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mux: ClockSrc::default(),
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ahb_pre: AHBPrescaler::DIV1,
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apb1_pre: APBPrescaler::DIV1,
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apb2_pre: APBPrescaler::DIV1,
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apb3_pre: APBPrescaler::DIV1,
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hsi48: false,
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voltage_range: VoltageScale::RANGE3,
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}
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ClockSrc::HSE(freq) => {
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RCC.cr().write(|w| w.set_hseon(true));
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while !RCC.cr().read().hserdy() {}
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}
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}
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freq.0
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}
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ClockSrc::HSI16 => {
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RCC.cr().write(|w| w.set_hsion(true));
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while !RCC.cr().read().hsirdy() {}
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pub(crate) unsafe fn init(config: Config) {
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// Ensure PWR peripheral clock is enabled
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RCC.ahb3enr().modify(|w| {
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w.set_pwren(true);
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});
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RCC.ahb3enr().read(); // synchronize
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HSI_FREQ.0
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}
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ClockSrc::PLL1R(src, m, n, div) => {
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let freq = match src {
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PllSrc::MSI(_) => {
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// TODO: enable MSI
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MSIRange::default().into()
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}
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PllSrc::HSE(hertz) => {
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// TODO: enable HSE
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hertz.0
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}
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PllSrc::HSI16 => {
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RCC.cr().write(|w| w.set_hsion(true));
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while !RCC.cr().read().hsirdy() {}
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// Set the requested power mode
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PWR.vosr().modify(|w| {
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w.set_vos(config.voltage_range);
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});
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while !PWR.vosr().read().vosrdy() {}
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HSI_FREQ.0
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}
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let sys_clk = match config.mux {
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ClockSrc::MSI(range) => config.init_msis(range),
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ClockSrc::HSE(freq) => config.init_hse(freq),
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ClockSrc::HSI16 => config.init_hsi16(),
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ClockSrc::PLL1R(pll) => {
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// Configure the PLL source
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let source_clk = match pll.source {
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PllSrc::MSIS(range) => config.init_msis(range),
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PllSrc::HSE(hertz) => config.init_hse(hertz),
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PllSrc::HSI16 => config.init_hsi16(),
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};
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// disable
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// Calculate the reference clock, which is the source divided by m
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let reference_clk = source_clk / (pll.m as u8 as u32 + 1);
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// Check limits per RM0456 § 11.4.6
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assert!(Hertz::mhz(4) <= reference_clk && reference_clk <= Hertz::mhz(16));
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// Calculate the PLL1 VCO clock and PLL1 R output clock
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let pll1_clk = reference_clk * (pll.n as u8 as u32);
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let pll1r_clk = pll1_clk / (pll.r as u8 as u32);
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// Check system clock per RM0456 § 11.4.9
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assert!(pll1r_clk <= Hertz::mhz(160));
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// Check PLL clocks per RM0456 § 11.4.10
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match config.voltage_range {
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VoltageScale::RANGE1 => {
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assert!(pll1_clk >= Hertz::mhz(128) && pll1_clk <= Hertz::mhz(544));
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assert!(pll1r_clk <= Hertz::mhz(208));
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}
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VoltageScale::RANGE2 => {
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assert!(pll1_clk >= Hertz::mhz(128) && pll1_clk <= Hertz::mhz(544));
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assert!(pll1r_clk <= Hertz::mhz(110));
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}
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VoltageScale::RANGE3 => {
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assert!(pll1_clk >= Hertz::mhz(128) && pll1_clk <= Hertz::mhz(330));
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assert!(pll1r_clk <= Hertz::mhz(55));
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}
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VoltageScale::RANGE4 => {
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panic!("PLL is unavailable in voltage range 4");
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}
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}
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// § 10.5.4: if we're targeting >= 55 MHz, we must configure PLL1MBOOST to a prescaler
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// value that results in an output between 4 and 16 MHz for the PWR EPOD boost
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let mboost = if pll1r_clk >= Hertz::mhz(55) {
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// source_clk can be up to 50 MHz, so there's just a few cases:
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if source_clk > Hertz::mhz(32) {
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// Divide by 4, giving EPOD 8-12.5 MHz
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Pllmboost::DIV4
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} else if source_clk > Hertz::mhz(16) {
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// Divide by 2, giving EPOD 8-16 MHz
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Pllmboost::DIV2
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} else {
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// Bypass, giving EPOD 4-16 MHz
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Pllmboost::BYPASS
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}
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} else {
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// Nothing to do
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Pllmboost::BYPASS
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};
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// Disable the PLL, and wait for it to disable
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RCC.cr().modify(|w| w.set_pllon(0, false));
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while RCC.cr().read().pllrdy(0) {}
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let vco = freq * n as u8 as u32;
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let pll_ck = vco / (div as u8 as u32 + 1);
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// Configure the PLL
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RCC.pll1cfgr().write(|w| {
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w.set_pllm(m.into());
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w.set_pllsrc(src.into());
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// Configure PLL1 source and prescaler
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w.set_pllsrc(pll.source.into());
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w.set_pllm(pll.m.into());
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// Configure PLL1 input frequncy range
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let input_range = if reference_clk <= Hertz::mhz(8) {
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Pllrge::FREQ_4TO8MHZ
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} else {
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Pllrge::FREQ_8TO16MHZ
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};
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w.set_pllrge(input_range);
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// Set the prescaler for PWR EPOD
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w.set_pllmboost(mboost);
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// Enable PLL1R output
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w.set_pllren(true);
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});
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// Configure the PLL divisors
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RCC.pll1divr().modify(|w| {
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w.set_pllr(div.to_div());
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w.set_plln(n.to_mul());
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// Set the VCO multiplier
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w.set_plln(pll.n.to_mul());
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// Set the R output divisor
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w.set_pllr(pll.r.to_div());
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});
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// Enable PLL
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// Do we need the EPOD booster to reach the target clock speed per § 10.5.4?
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if pll1r_clk >= Hertz::mhz(55) {
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// Enable the booster
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PWR.vosr().modify(|w| {
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w.set_boosten(true);
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});
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while !PWR.vosr().read().boostrdy() {}
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}
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// Enable the PLL
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RCC.cr().modify(|w| w.set_pllon(0, true));
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while !RCC.cr().read().pllrdy(0) {}
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pll_ck
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pll1r_clk
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}
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};
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}
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.0;
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if config.hsi48 {
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RCC.cr().modify(|w| w.set_hsi48on(true));
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while !RCC.cr().read().hsi48rdy() {}
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}
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// TODO make configurable
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let power_vos = VoltageScale::RANGE3;
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// states and programming delay
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let wait_states = match power_vos {
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// The clock source is ready
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// Calculate and set the flash wait states
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let wait_states = match config.voltage_range {
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// VOS 1 range VCORE 1.26V - 1.40V
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VoltageScale::RANGE1 => {
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if sys_clk < 32_000_000 {
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@ -335,21 +498,34 @@ pub(crate) unsafe fn init(config: Config) {
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}
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}
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};
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|
||||
FLASH.acr().modify(|w| {
|
||||
w.set_latency(wait_states);
|
||||
});
|
||||
|
||||
// Switch the system clock source
|
||||
RCC.cfgr1().modify(|w| {
|
||||
w.set_sw(config.mux.into());
|
||||
});
|
||||
|
||||
// RM0456 § 11.4.9 specifies maximum bus frequencies per voltage range, but the maximum bus
|
||||
// frequency for each voltage range exactly matches the maximum permitted PLL output frequency.
|
||||
// Given that:
|
||||
//
|
||||
// 1. Any bus frequency can never exceed the system clock frequency;
|
||||
// 2. We checked the PLL output frequency if we're using it as a system clock;
|
||||
// 3. The maximum HSE frequencies at each voltage range are lower than the bus limits, and
|
||||
// we checked the HSE frequency if configured as a system clock; and
|
||||
// 4. The maximum frequencies from the other clock sources are lower than the lowest bus
|
||||
// frequency limit
|
||||
//
|
||||
// ...then we do not need to perform additional bus-related frequency checks.
|
||||
|
||||
// Configure the bus prescalers
|
||||
RCC.cfgr2().modify(|w| {
|
||||
w.set_hpre(config.ahb_pre.into());
|
||||
w.set_ppre1(config.apb1_pre.into());
|
||||
w.set_ppre2(config.apb2_pre.into());
|
||||
});
|
||||
|
||||
RCC.cfgr3().modify(|w| {
|
||||
w.set_ppre3(config.apb3_pre.into());
|
||||
});
|
||||
|
||||
@ -23,7 +23,12 @@ async fn main(_spawner: Spawner) {
|
||||
info!("Hello World!");
|
||||
|
||||
let mut config = Config::default();
|
||||
config.rcc.mux = ClockSrc::PLL1R(PllSrc::HSI16, PllM::Div2, PllN::Mul10, PllClkDiv::NotDivided);
|
||||
config.rcc.mux = ClockSrc::PLL1R(PllConfig {
|
||||
source: PllSrc::HSI16,
|
||||
m: PllM::Div2,
|
||||
n: PllN::Mul10,
|
||||
r: PllClkDiv::NotDivided,
|
||||
});
|
||||
//config.rcc.mux = ClockSrc::MSI(MSIRange::Range48mhz);
|
||||
config.rcc.hsi48 = true;
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user