Merge pull request #1721 from MabezDev/rtc-f2-dont-reset-bd
stm32f2: Avoid resetting RTC backup domain
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commit
3c3a1d89b5
@ -39,9 +39,8 @@ impl<'d, T: Instance> super::Rtc<'d, T> {
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let rtcsel = reg.rtcsel().to_bits();
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let rtcsel = reg.rtcsel().to_bits();
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if !reg.rtcen() || rtcsel != clock_config {
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if !reg.rtcen() || rtcsel != clock_config {
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#[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
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#[cfg(not(any(rtc_v2l0, rtc_v2l1, rtc_v2f2)))]
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crate::pac::RCC.bdcr().modify(|w| w.set_bdrst(true));
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crate::pac::RCC.bdcr().modify(|w| w.set_bdrst(true));
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#[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
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#[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
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let cr = crate::pac::RCC.bdcr();
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let cr = crate::pac::RCC.bdcr();
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#[cfg(any(rtc_v2l0, rtc_v2l1))]
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#[cfg(any(rtc_v2l0, rtc_v2l1))]
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@ -201,6 +200,11 @@ impl sealed::Instance for crate::peripherals::RTC {
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// read to allow the pwr clock to enable
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// read to allow the pwr clock to enable
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crate::pac::PWR.cr1().read();
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crate::pac::PWR.cr1().read();
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}
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}
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#[cfg(any(rtc_v2f2))]
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{
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crate::pac::RCC.apb1enr().modify(|w| w.set_pwren(true));
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crate::pac::PWR.cr().read();
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}
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}
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}
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fn read_backup_register(rtc: &Rtc, register: usize) -> Option<u32> {
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fn read_backup_register(rtc: &Rtc, register: usize) -> Option<u32> {
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