issue 2059 fix build errors in ci
This commit is contained in:
parent
6c2ad332e8
commit
3c58465e30
@ -1,6 +1,6 @@
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//! Basic Direct Memory Acccess (BDMA)
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//! Basic Direct Memory Acccess (BDMA)
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use core::future::Future;
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use core::future::{poll_fn, Future};
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use core::pin::Pin;
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use core::pin::Pin;
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use core::sync::atomic::{fence, AtomicUsize, Ordering};
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use core::sync::atomic::{fence, AtomicUsize, Ordering};
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use core::task::{Context, Poll, Waker};
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use core::task::{Context, Poll, Waker};
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@ -431,6 +431,45 @@ impl<'a, C: Channel> DmaCtrl for DmaCtrlImpl<'a, C> {
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}
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}
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}
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}
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struct RingBuffer {}
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impl RingBuffer {
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fn is_running(ch: &pac::bdma::Ch) -> bool {
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ch.cr().read().en()
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}
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fn request_stop(ch: &pac::bdma::Ch) {
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// Disable the channel. Keep the IEs enabled so the irqs still fire.
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// If the channel is enabled and transfer is not completed, we need to perform
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// two separate write access to the CR register to disable the channel.
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ch.cr().write(|w| {
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w.set_teie(true);
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w.set_htie(true);
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w.set_tcie(true);
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});
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}
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async fn stop(ch: &pac::bdma::Ch, set_waker: &mut dyn FnMut(&Waker)) {
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use core::sync::atomic::compiler_fence;
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Self::request_stop(ch);
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//wait until cr.susp reads as true
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poll_fn(|cx| {
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set_waker(cx.waker());
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compiler_fence(Ordering::SeqCst);
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if !Self::is_running(ch) {
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Poll::Ready(())
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} else {
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Poll::Pending
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}
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})
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.await
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}
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}
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/// Ringbuffer for reading data using DMA circular mode.
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/// Ringbuffer for reading data using DMA circular mode.
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pub struct ReadableRingBuffer<'a, C: Channel, W: Word> {
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pub struct ReadableRingBuffer<'a, C: Channel, W: Word> {
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cr: regs::Cr,
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cr: regs::Cr,
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@ -508,6 +547,13 @@ impl<'a, C: Channel, W: Word> ReadableRingBuffer<'a, C, W> {
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self.ringbuf.clear(&mut DmaCtrlImpl(self.channel.reborrow()));
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self.ringbuf.clear(&mut DmaCtrlImpl(self.channel.reborrow()));
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}
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}
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pub async fn stop(&mut self) {
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RingBuffer::stop(&self.channel.regs().ch(self.channel.num()), &mut |waker| {
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self.set_waker(waker)
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})
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.await
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}
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/// Read elements from the ring buffer
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/// Read elements from the ring buffer
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/// Return a tuple of the length read and the length remaining in the buffer
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/// Return a tuple of the length read and the length remaining in the buffer
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/// If not all of the elements were read, then there will be some elements in the buffer remaining
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/// If not all of the elements were read, then there will be some elements in the buffer remaining
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@ -557,16 +603,7 @@ impl<'a, C: Channel, W: Word> ReadableRingBuffer<'a, C, W> {
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///
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///
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/// This doesn't immediately stop the transfer, you have to wait until [`is_running`](Self::is_running) returns false.
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/// This doesn't immediately stop the transfer, you have to wait until [`is_running`](Self::is_running) returns false.
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pub fn request_stop(&mut self) {
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pub fn request_stop(&mut self) {
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let ch = self.channel.regs().ch(self.channel.num());
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RingBuffer::request_stop(&self.channel.regs().ch(self.channel.num()));
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// Disable the channel. Keep the IEs enabled so the irqs still fire.
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// If the channel is enabled and transfer is not completed, we need to perform
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// two separate write access to the CR register to disable the channel.
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ch.cr().write(|w| {
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w.set_teie(true);
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w.set_htie(true);
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w.set_tcie(true);
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});
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}
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}
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/// Return whether DMA is still running.
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/// Return whether DMA is still running.
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@ -574,8 +611,7 @@ impl<'a, C: Channel, W: Word> ReadableRingBuffer<'a, C, W> {
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/// If this returns `false`, it can be because either the transfer finished, or
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/// If this returns `false`, it can be because either the transfer finished, or
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/// it was requested to stop early with [`request_stop`](Self::request_stop).
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/// it was requested to stop early with [`request_stop`](Self::request_stop).
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pub fn is_running(&mut self) -> bool {
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pub fn is_running(&mut self) -> bool {
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let ch = self.channel.regs().ch(self.channel.num());
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RingBuffer::is_running(&self.channel.regs().ch(self.channel.num()))
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ch.cr().read().en()
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}
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}
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}
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}
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@ -666,6 +702,20 @@ impl<'a, C: Channel, W: Word> WritableRingBuffer<'a, C, W> {
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self.ringbuf.clear(&mut DmaCtrlImpl(self.channel.reborrow()));
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self.ringbuf.clear(&mut DmaCtrlImpl(self.channel.reborrow()));
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}
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}
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/// Write elements directly to the raw buffer.
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/// This can be used to fill the buffer before starting the DMA transfer.
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#[allow(dead_code)]
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pub fn write_immediate(&mut self, buf: &[W]) -> Result<(usize, usize), OverrunError> {
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self.ringbuf.write_immediate(buf)
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}
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pub async fn stop(&mut self) {
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RingBuffer::stop(&self.channel.regs().ch(self.channel.num()), &mut |waker| {
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self.set_waker(waker)
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})
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.await
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}
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/// Write elements to the ring buffer
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/// Write elements to the ring buffer
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/// Return a tuple of the length written and the length remaining in the buffer
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/// Return a tuple of the length written and the length remaining in the buffer
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pub fn write(&mut self, buf: &[W]) -> Result<(usize, usize), OverrunError> {
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pub fn write(&mut self, buf: &[W]) -> Result<(usize, usize), OverrunError> {
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@ -702,16 +752,7 @@ impl<'a, C: Channel, W: Word> WritableRingBuffer<'a, C, W> {
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///
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///
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/// This doesn't immediately stop the transfer, you have to wait until [`is_running`](Self::is_running) returns false.
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/// This doesn't immediately stop the transfer, you have to wait until [`is_running`](Self::is_running) returns false.
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pub fn request_stop(&mut self) {
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pub fn request_stop(&mut self) {
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let ch = self.channel.regs().ch(self.channel.num());
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RingBuffer::request_stop(&self.channel.regs().ch(self.channel.num()));
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// Disable the channel. Keep the IEs enabled so the irqs still fire.
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// If the channel is enabled and transfer is not completed, we need to perform
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// two separate write access to the CR register to disable the channel.
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ch.cr().write(|w| {
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w.set_teie(true);
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w.set_htie(true);
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w.set_tcie(true);
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});
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}
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}
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/// Return whether DMA is still running.
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/// Return whether DMA is still running.
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@ -719,8 +760,7 @@ impl<'a, C: Channel, W: Word> WritableRingBuffer<'a, C, W> {
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/// If this returns `false`, it can be because either the transfer finished, or
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/// If this returns `false`, it can be because either the transfer finished, or
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/// it was requested to stop early with [`request_stop`](Self::request_stop).
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/// it was requested to stop early with [`request_stop`](Self::request_stop).
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pub fn is_running(&mut self) -> bool {
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pub fn is_running(&mut self) -> bool {
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let ch = self.channel.regs().ch(self.channel.num());
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RingBuffer::is_running(&self.channel.regs().ch(self.channel.num()))
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ch.cr().read().en()
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}
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}
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}
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}
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@ -1,4 +1,4 @@
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use core::future::Future;
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use core::future::{poll_fn, Future};
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use core::marker::PhantomData;
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use core::marker::PhantomData;
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use core::pin::Pin;
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use core::pin::Pin;
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use core::sync::atomic::{fence, AtomicUsize, Ordering};
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use core::sync::atomic::{fence, AtomicUsize, Ordering};
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@ -668,6 +668,42 @@ impl<'a, C: Channel> DmaCtrl for DmaCtrlImpl<'a, C> {
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}
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}
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}
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}
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struct RingBuffer {}
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impl RingBuffer {
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fn is_running(ch: &pac::dma::St) -> bool {
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ch.cr().read().en()
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}
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fn request_stop(ch: &pac::dma::St) {
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ch.cr().write(|w| {
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w.set_teie(true);
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w.set_htie(true);
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w.set_tcie(true);
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});
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}
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async fn stop(ch: &pac::dma::St, set_waker: &mut dyn FnMut(&Waker)) {
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use core::sync::atomic::compiler_fence;
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Self::request_stop(ch);
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//wait until cr.susp reads as true
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poll_fn(|cx| {
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set_waker(cx.waker());
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compiler_fence(Ordering::SeqCst);
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if !Self::is_running(ch) {
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Poll::Ready(())
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} else {
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Poll::Pending
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}
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})
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.await
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}
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}
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/// Ringbuffer for receiving data using DMA circular mode.
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/// Ringbuffer for receiving data using DMA circular mode.
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pub struct ReadableRingBuffer<'a, C: Channel, W: Word> {
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pub struct ReadableRingBuffer<'a, C: Channel, W: Word> {
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cr: regs::Cr,
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cr: regs::Cr,
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@ -755,6 +791,17 @@ impl<'a, C: Channel, W: Word> ReadableRingBuffer<'a, C, W> {
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ch.cr().write_value(self.cr);
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ch.cr().write_value(self.cr);
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}
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}
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pub async fn stop(&mut self) {
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RingBuffer::stop(&self.channel.regs().st(self.channel.num()), &mut |waker| {
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self.set_waker(waker)
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})
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.await
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}
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pub fn resume(&mut self) {
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self.start();
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}
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/// Clear all data in the ring buffer.
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/// Clear all data in the ring buffer.
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pub fn clear(&mut self) {
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pub fn clear(&mut self) {
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self.ringbuf.clear(&mut DmaCtrlImpl(self.channel.reborrow()));
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self.ringbuf.clear(&mut DmaCtrlImpl(self.channel.reborrow()));
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@ -930,6 +977,13 @@ impl<'a, C: Channel, W: Word> WritableRingBuffer<'a, C, W> {
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ch.cr().write_value(self.cr);
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ch.cr().write_value(self.cr);
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}
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}
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pub async fn stop(&mut self) {
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RingBuffer::stop(&self.channel.regs().st(self.channel.num()), &mut |waker| {
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self.set_waker(waker)
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})
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.await
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}
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/// Clear all data in the ring buffer.
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/// Clear all data in the ring buffer.
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pub fn clear(&mut self) {
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pub fn clear(&mut self) {
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self.ringbuf.clear(&mut DmaCtrlImpl(self.channel.reborrow()));
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self.ringbuf.clear(&mut DmaCtrlImpl(self.channel.reborrow()));
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@ -937,14 +991,9 @@ impl<'a, C: Channel, W: Word> WritableRingBuffer<'a, C, W> {
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/// Write elements directly to the raw buffer.
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/// Write elements directly to the raw buffer.
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/// This can be used to fill the buffer before starting the DMA transfer.
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/// This can be used to fill the buffer before starting the DMA transfer.
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#[allow(dead_code)]
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pub fn write_immediate(&mut self, buf: &[W]) -> Result<(usize, usize), OverrunError> {
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pub fn write_immediate(&mut self, buf: &[W]) -> Result<(usize, usize), OverrunError> {
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self.ringbuf.write_immediate(
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self.ringbuf.write_immediate(buf)
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&mut DmaCtrlImpl {
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channel: self.channel.reborrow(),
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word_size: W::size(),
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},
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buf,
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)
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}
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}
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/// Write elements from the ring buffer
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/// Write elements from the ring buffer
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@ -491,7 +491,7 @@ impl RingBuffer {
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});
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});
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}
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}
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async fn suspend(ch: &pac::gpdma::Channel, set_waker: &mut dyn FnMut(&Waker)) {
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async fn stop(ch: &pac::gpdma::Channel, set_waker: &mut dyn FnMut(&Waker)) {
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use core::sync::atomic::compiler_fence;
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use core::sync::atomic::compiler_fence;
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Self::request_suspend(ch);
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Self::request_suspend(ch);
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@ -504,17 +504,15 @@ impl RingBuffer {
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let cr = ch.cr().read();
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let cr = ch.cr().read();
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if cr.susp() {
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if cr.susp() {
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defmt::info!("Ready {}", cr.susp());
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Poll::Ready(())
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Poll::Ready(())
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} else {
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} else {
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defmt::info!("still pending {}", cr.susp());
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Poll::Pending
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Poll::Pending
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}
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}
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})
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})
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.await
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.await
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}
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}
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fn resume(ch: &pac::gpdma::Channel) {
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fn start(ch: &pac::gpdma::Channel) {
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Self::clear_irqs(ch);
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Self::clear_irqs(ch);
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ch.cr().modify(|w| {
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ch.cr().modify(|w| {
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w.set_susp(false);
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w.set_susp(false);
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@ -534,7 +532,7 @@ pub struct ReadableRingBuffer<'a, C: Channel, W: Word> {
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}
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}
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impl<'a, C: Channel, W: Word> ReadableRingBuffer<'a, C, W> {
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impl<'a, C: Channel, W: Word> ReadableRingBuffer<'a, C, W> {
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pub unsafe fn new_read(
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pub unsafe fn new(
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channel: impl Peripheral<P = C> + 'a,
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channel: impl Peripheral<P = C> + 'a,
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request: Request,
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request: Request,
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peri_addr: *mut W,
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peri_addr: *mut W,
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@ -564,25 +562,21 @@ impl<'a, C: Channel, W: Word> ReadableRingBuffer<'a, C, W> {
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pub fn start(&mut self) {
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pub fn start(&mut self) {
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let ch = &self.channel.regs().ch(self.channel.num());
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let ch = &self.channel.regs().ch(self.channel.num());
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RingBuffer::clear_irqs(ch);
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RingBuffer::start(ch);
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ch.cr().modify(|w| w.set_en(true));
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//ch.cr().modify(|w| w.set_en(true));
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}
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}
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pub fn request_stop(&mut self, ch: &pac::gpdma::Channel) {
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pub fn request_stop(&mut self) {
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ch.cr().modify(|w| w.set_en(false));
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RingBuffer::request_suspend(&self.channel.regs().ch(self.channel.num()));
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}
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}
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pub async fn suspend(&mut self) {
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pub async fn stop(&mut self) {
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RingBuffer::suspend(&self.channel.regs().ch(self.channel.num()), &mut |waker| {
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RingBuffer::stop(&self.channel.regs().ch(self.channel.num()), &mut |waker| {
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self.set_waker(waker)
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self.set_waker(waker)
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})
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})
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.await
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.await
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}
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}
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pub fn resume(&mut self) {
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RingBuffer::resume(&self.channel.regs().ch(self.channel.num()));
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}
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pub fn clear(&mut self) {
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pub fn clear(&mut self) {
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self.ringbuf.clear(&mut DmaCtrlImpl {
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self.ringbuf.clear(&mut DmaCtrlImpl {
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channel: self.channel.reborrow(),
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channel: self.channel.reborrow(),
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@ -648,7 +642,7 @@ impl<'a, C: Channel, W: Word> ReadableRingBuffer<'a, C, W> {
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impl<'a, C: Channel, W: Word> Drop for ReadableRingBuffer<'a, C, W> {
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impl<'a, C: Channel, W: Word> Drop for ReadableRingBuffer<'a, C, W> {
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fn drop(&mut self) {
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fn drop(&mut self) {
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RingBuffer::request_suspend(&self.channel.regs().ch(self.channel.num()));
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self.request_stop();
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while self.is_running() {}
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while self.is_running() {}
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// "Subsequent reads and writes cannot be moved ahead of preceding reads."
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// "Subsequent reads and writes cannot be moved ahead of preceding reads."
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@ -663,7 +657,7 @@ pub struct WritableRingBuffer<'a, C: Channel, W: Word> {
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}
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}
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impl<'a, C: Channel, W: Word> WritableRingBuffer<'a, C, W> {
|
impl<'a, C: Channel, W: Word> WritableRingBuffer<'a, C, W> {
|
||||||
pub unsafe fn new_write(
|
pub unsafe fn new(
|
||||||
channel: impl Peripheral<P = C> + 'a,
|
channel: impl Peripheral<P = C> + 'a,
|
||||||
request: Request,
|
request: Request,
|
||||||
peri_addr: *mut W,
|
peri_addr: *mut W,
|
||||||
@ -692,26 +686,28 @@ impl<'a, C: Channel, W: Word> WritableRingBuffer<'a, C, W> {
|
|||||||
}
|
}
|
||||||
|
|
||||||
pub fn start(&mut self) {
|
pub fn start(&mut self) {
|
||||||
self.resume();
|
RingBuffer::start(&self.channel.regs().ch(self.channel.num()));
|
||||||
}
|
}
|
||||||
|
|
||||||
pub async fn suspend(&mut self) {
|
pub async fn stop(&mut self) {
|
||||||
RingBuffer::suspend(&self.channel.regs().ch(self.channel.num()), &mut |waker| {
|
RingBuffer::stop(&self.channel.regs().ch(self.channel.num()), &mut |waker| {
|
||||||
self.set_waker(waker)
|
self.set_waker(waker)
|
||||||
})
|
})
|
||||||
.await
|
.await
|
||||||
}
|
}
|
||||||
|
|
||||||
pub fn resume(&mut self) {
|
|
||||||
RingBuffer::resume(&self.channel.regs().ch(self.channel.num()));
|
|
||||||
}
|
|
||||||
|
|
||||||
pub fn request_stop(&mut self) {
|
pub fn request_stop(&mut self) {
|
||||||
// reads can be stopped by disabling the enable flag
|
// reads can be stopped by disabling the enable flag
|
||||||
let ch = &self.channel.regs().ch(self.channel.num());
|
let ch = &self.channel.regs().ch(self.channel.num());
|
||||||
ch.cr().modify(|w| w.set_en(false));
|
ch.cr().modify(|w| w.set_en(false));
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/// Write elements directly to the raw buffer.
|
||||||
|
/// This can be used to fill the buffer before starting the DMA transfer.
|
||||||
|
pub fn write_immediate(&mut self, buf: &[W]) -> Result<(usize, usize), OverrunError> {
|
||||||
|
self.ringbuf.write_immediate(buf)
|
||||||
|
}
|
||||||
|
|
||||||
pub fn clear(&mut self) {
|
pub fn clear(&mut self) {
|
||||||
self.ringbuf.clear(&mut DmaCtrlImpl {
|
self.ringbuf.clear(&mut DmaCtrlImpl {
|
||||||
channel: self.channel.reborrow(),
|
channel: self.channel.reborrow(),
|
||||||
@ -731,18 +727,6 @@ impl<'a, C: Channel, W: Word> WritableRingBuffer<'a, C, W> {
|
|||||||
)
|
)
|
||||||
}
|
}
|
||||||
|
|
||||||
/// Write elements directly to the raw buffer.
|
|
||||||
/// This can be used to fill the buffer before starting the DMA transfer.
|
|
||||||
pub fn write_immediate(&mut self, buf: &[W]) -> Result<(usize, usize), OverrunError> {
|
|
||||||
self.ringbuf.write_immediate(
|
|
||||||
&mut DmaCtrlImpl {
|
|
||||||
channel: self.channel.reborrow(),
|
|
||||||
word_size: W::size(),
|
|
||||||
},
|
|
||||||
buf,
|
|
||||||
)
|
|
||||||
}
|
|
||||||
|
|
||||||
/// Write an exact number of elements to the ringbuffer.
|
/// Write an exact number of elements to the ringbuffer.
|
||||||
pub async fn write_exact(&mut self, buffer: &[W]) -> Result<usize, OverrunError> {
|
pub async fn write_exact(&mut self, buffer: &[W]) -> Result<usize, OverrunError> {
|
||||||
self.ringbuf
|
self.ringbuf
|
||||||
@ -776,7 +760,7 @@ impl<'a, C: Channel, W: Word> WritableRingBuffer<'a, C, W> {
|
|||||||
|
|
||||||
impl<'a, C: Channel, W: Word> Drop for WritableRingBuffer<'a, C, W> {
|
impl<'a, C: Channel, W: Word> Drop for WritableRingBuffer<'a, C, W> {
|
||||||
fn drop(&mut self) {
|
fn drop(&mut self) {
|
||||||
RingBuffer::request_suspend(&self.channel.regs().ch(self.channel.num()));
|
self.request_stop();
|
||||||
while self.is_running() {}
|
while self.is_running() {}
|
||||||
|
|
||||||
// "Subsequent reads and writes cannot be moved ahead of preceding reads."
|
// "Subsequent reads and writes cannot be moved ahead of preceding reads."
|
||||||
|
@ -264,7 +264,7 @@ impl<'a, W: Word> WritableDmaRingBuffer<'a, W> {
|
|||||||
}
|
}
|
||||||
|
|
||||||
/// Write elements directl to the buffer. This should be done before the DMA is started.
|
/// Write elements directl to the buffer. This should be done before the DMA is started.
|
||||||
pub fn write_immediate(&mut self, dma: &mut impl DmaCtrl, buffer: &[W]) -> Result<(usize, usize), OverrunError> {
|
pub fn write_immediate(&mut self, buffer: &[W]) -> Result<(usize, usize), OverrunError> {
|
||||||
if self.end != 0 {
|
if self.end != 0 {
|
||||||
return Err(OverrunError);
|
return Err(OverrunError);
|
||||||
}
|
}
|
||||||
|
@ -1008,17 +1008,10 @@ impl<'d, T: Instance, C: Channel, W: word::Word> SubBlock<'d, T, C, W> {
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
pub async fn suspend(&mut self) {
|
pub async fn stop(&mut self) {
|
||||||
match &mut self.ring_buffer {
|
match &mut self.ring_buffer {
|
||||||
RingBuffer::Writable(buffer) => buffer.suspend().await,
|
RingBuffer::Writable(buffer) => buffer.stop().await,
|
||||||
RingBuffer::Readable(buffer) => buffer.suspend().await,
|
RingBuffer::Readable(buffer) => buffer.stop().await,
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
pub fn resume(&mut self) {
|
|
||||||
match &mut self.ring_buffer {
|
|
||||||
RingBuffer::Writable(buffer) => buffer.resume(),
|
|
||||||
RingBuffer::Readable(buffer) => buffer.resume(),
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -28,6 +28,8 @@ async fn main(_spawner: Spawner) {
|
|||||||
m: Pllm::DIV2,
|
m: Pllm::DIV2,
|
||||||
n: Plln::MUL10,
|
n: Plln::MUL10,
|
||||||
r: Plldiv::DIV1,
|
r: Plldiv::DIV1,
|
||||||
|
p: Plldiv::DIV1,
|
||||||
|
q: Plldiv::DIV1,
|
||||||
});
|
});
|
||||||
config.rcc.hsi48 = Some(Hsi48Config { sync_from_usb: true }); // needed for USB
|
config.rcc.hsi48 = Some(Hsi48Config { sync_from_usb: true }); // needed for USB
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user