add dma transfer example
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@ -17,20 +17,23 @@ use cortex_m::singleton;
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use crate::hal::dma::config::DmaConfig;
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use crate::hal::dma::config::DmaConfig;
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use crate::hal::dma::{Channel4, PeripheralToMemory, Stream2, StreamsTuple, Transfer};
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use crate::hal::dma::{Channel4, PeripheralToMemory, Stream2, StreamsTuple, Transfer};
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use crate::hal::gpio::{Alternate, AF10, AF7, AF9};
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use crate::hal::gpio::{Alternate, AF10, AF7, AF9};
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use crate::hal::gpio::{
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use crate::hal::gpio::{Floating, Input, Output, PushPull};
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Floating, Input, Output, Pin as GpioPin, Port as GpioPort, PushPull, Rx, Tx,
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use crate::hal::rcc::Clocks;
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use crate::hal::serial::config::{
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Config as SerialConfig, DmaConfig as SerialDmaConfig, Parity, StopBits, WordLength,
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};
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};
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use crate::hal::serial::{DmaConfig, Event, Parity, StopBits, WordLength};
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use crate::hal::serial::Serial;
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use crate::hal::time::Bps;
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use crate::interrupt;
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use crate::interrupt;
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use crate::interrupt::CriticalSection;
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use crate::interrupt::CriticalSection;
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use crate::pac::{uarte0, Interrupt, UARTE0, USART1};
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use crate::pac::Interrupt;
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#[cfg(any(feature = "52833", feature = "52840", feature = "9160"))]
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use crate::pac::{DMA2, USART1};
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use crate::pac::{DMA2, UARTE1};
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use embedded_hal::digital::v2::OutputPin;
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use embedded_hal::digital::v2::OutputPin;
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// Re-export SVD variants to allow user to directly set values
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// Re-export SVD variants to allow user to directly set values
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pub use uarte0::{baudrate::BAUDRATE_A as Baudrate, config::PARITY_A as Parity};
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// pub use uarte0::{baudrate::BAUDRATE_A as Baudrate, config::PARITY_A as Parity};
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use embassy::io::{AsyncBufRead, AsyncWrite, Result};
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use embassy::io::{AsyncBufRead, AsyncWrite, Result};
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use embassy::util::WakerStore;
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use embassy::util::WakerStore;
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@ -171,26 +174,29 @@ fn port_bit(port: GpioPort) -> bool {
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}
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}
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impl<T: Instance> Uarte<T> {
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impl<T: Instance> Uarte<T> {
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pub fn new(uarte: T, mut pins: Pins, parity: Parity, baudrate: Baudrate) -> Self {
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pub fn new(uarte: T, mut pins: Pins, parity: Parity, baudrate: Bps, clocks: Clocks) -> Self {
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// Select pins
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// Select pins
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// Serial<USART1, (PA9<Alternate<AF7>>, PA10<Alternate<AF7>>)>
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// Serial<USART1, (PA9<Alternate<AF7>>, PA10<Alternate<AF7>>)>
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let mut serial = Serial::usart1(
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let mut serial = Serial::usart1(
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dp.USART1,
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pins.usart,
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(pins.txd, pins.rxd),
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(pins.txd, pins.rxd),
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Config {
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SerialConfig {
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baudrate: 9600.bps(),
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baudrate: baudrate,
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wordlength: WordLength::DataBits8,
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wordlength: WordLength::DataBits8,
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parity: Parity::ParityNone,
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parity: Parity::ParityNone,
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stopbits: StopBits::STOP1,
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stopbits: StopBits::STOP1,
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dma: DmaConfig::TxRx,
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dma: SerialDmaConfig::TxRx,
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},
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},
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clocks,
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clocks,
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)
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)
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.unwrap();
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.unwrap();
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let isr = pins.dma.hisr;
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// self.isr().$tcifX().bit_is_clear()
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// Enable interrupts
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// Enable interrupts
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serial.listen(Event::Txe);
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// serial.listen(Event::Txe);
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serial.listen(Event::Txe);
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// serial.listen(Event::Txe);
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// TODO: Enable idle interrupt? Use DMA interrupt?
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// TODO: Enable idle interrupt? Use DMA interrupt?
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@ -207,13 +213,6 @@ impl<T: Instance> Uarte<T> {
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Taken from https://gist.github.com/thalesfragoso/a07340c5df6eee3b04c42fdc69ecdcb1
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Taken from https://gist.github.com/thalesfragoso/a07340c5df6eee3b04c42fdc69ecdcb1
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*/
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*/
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// configure dma transfer
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let stream_7 = StreamsTuple::new(pins.dma).7;
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let config = DmaConfig::default()
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.transfer_complete_interrupt(true)
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.memory_increment(true)
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.double_buffer(true);
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// let rcc = unsafe { &*RCC::ptr() };
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// let rcc = unsafe { &*RCC::ptr() };
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// rcc.apb2enr.modify(|_, w| w.adc1en().enabled());
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// rcc.apb2enr.modify(|_, w| w.adc1en().enabled());
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// rcc.apb2rstr.modify(|_, w| w.adcrst().set_bit());
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// rcc.apb2rstr.modify(|_, w| w.adcrst().set_bit());
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@ -230,18 +229,6 @@ impl<T: Instance> Uarte<T> {
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// .enabled()
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// .enabled()
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// });
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// });
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let first_buffer = singleton!(: [u8; 128] = [0; 128]).unwrap();
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let second_buffer = singleton!(: [u8; 128] = [0; 128]).unwrap();
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let triple_buffer = Some(singleton!(: [u8; 128] = [0; 128]).unwrap());
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let transfer = Transfer::init(
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stream_7,
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pins.usart,
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first_buffer,
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Some(second_buffer),
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config,
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);
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// Configure
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// Configure
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//let hardware_flow_control = pins.rts.is_some() && pins.cts.is_some();
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//let hardware_flow_control = pins.rts.is_some() && pins.cts.is_some();
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//uarte
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//uarte
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@ -510,6 +497,25 @@ impl<T: Instance> UarteState<T> {
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}
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}
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TxState::Transmitting(n) => {
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TxState::Transmitting(n) => {
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trace!(" irq_tx: in state Transmitting");
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trace!(" irq_tx: in state Transmitting");
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// Start the DMA transfer
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// See https://github.com/mwkroening/async-stm32f1xx/blob/78c46d1bff124eae4ebc7a2f4d40e6ed74def8b5/src/serial.rs#L118-L129
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// https://github.com/stm32-rs/stm32f1xx-hal/blob/68fd3d6f282173816fd3181e795988d314cb17d0/src/serial.rs#L649-L671
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let first_buffer = singleton!(: [u8; 128] = [0; 128]).unwrap();
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let second_buffer = singleton!(: [u8; 128] = [0; 128]).unwrap();
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let triple_buffer = Some(singleton!(: [u8; 128] = [0; 128]).unwrap());
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let transfer = Transfer::init(
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StreamsTuple::new(pins.dma).7,
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pins.usart,
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first_buffer,
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Some(second_buffer),
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DmaConfig::default()
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.transfer_complete_interrupt(true)
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.memory_increment(true)
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.double_buffer(true),
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);
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if self.inner.events_endtx.read().bits() != 0 {
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if self.inner.events_endtx.read().bits() != 0 {
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self.inner.events_endtx.reset();
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self.inner.events_endtx.reset();
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