stm32/dma: impl all variants
This commit is contained in:
Dario Nieuwenhuis
committed by
Bob McWhirter
Bob McWhirter
parent
69fb1b5418
commit
3d1391ef2d
222
embassy-stm32/src/dma/bdma.rs
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222
embassy-stm32/src/dma/bdma.rs
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@ -0,0 +1,222 @@
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#![macro_use]
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use core::future::Future;
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use core::task::Poll;
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use atomic_polyfill::{AtomicU8, Ordering};
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use embassy::interrupt::{Interrupt, InterruptExt};
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use embassy::util::{AtomicWaker, OnDrop};
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use futures::future::poll_fn;
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use crate::dma::{Channel, Request};
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use crate::interrupt;
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use crate::pac;
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use crate::pac::bdma::vals;
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use crate::rcc::sealed::RccPeripheral;
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const CH_COUNT: usize = pac::peripheral_count!(bdma) * 8;
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const CH_STATUS_NONE: u8 = 0;
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const CH_STATUS_COMPLETED: u8 = 1;
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const CH_STATUS_ERROR: u8 = 2;
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struct State {
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ch_wakers: [AtomicWaker; CH_COUNT],
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ch_status: [AtomicU8; CH_COUNT],
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}
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impl State {
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const fn new() -> Self {
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const AW: AtomicWaker = AtomicWaker::new();
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const AU: AtomicU8 = AtomicU8::new(CH_STATUS_NONE);
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Self {
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ch_wakers: [AW; CH_COUNT],
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ch_status: [AU; CH_COUNT],
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}
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}
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}
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static STATE: State = State::new();
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#[allow(unused)]
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pub(crate) async unsafe fn do_transfer(
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dma: pac::bdma::Dma,
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channel_number: u8,
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state_number: u8,
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request: Request,
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dir: vals::Dir,
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peri_addr: *const u8,
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mem_addr: *mut u8,
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mem_len: usize,
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#[cfg(dmamux)] dmamux_regs: pac::dmamux::Dmamux,
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#[cfg(dmamux)] dmamux_ch_num: u8,
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) {
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// ndtr is max 16 bits.
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assert!(mem_len <= 0xFFFF);
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let ch = dma.ch(channel_number as _);
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// Reset status
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// Generate a DMB here to flush the store buffer (M7) before enabling the DMA
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STATE.ch_status[state_number as usize].store(CH_STATUS_NONE, Ordering::Release);
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let on_drop = OnDrop::new(|| unsafe {
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ch.cr().modify(|w| {
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w.set_tcie(false);
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w.set_teie(false);
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w.set_en(false);
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});
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while ch.cr().read().en() {}
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});
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#[cfg(dmamux)]
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super::dmamux::configure_dmamux(dmamux_regs, dmamux_ch_num, request);
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#[cfg(bdma_v2)]
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critical_section::with(|_| {
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dma.cselr()
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.modify(|w| w.set_cs(channel_number as _, request))
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});
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ch.par().write_value(peri_addr as u32);
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ch.mar().write_value(mem_addr as u32);
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ch.ndtr().write(|w| w.set_ndt(mem_len as u16));
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ch.cr().write(|w| {
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w.set_psize(vals::Size::BITS8);
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w.set_msize(vals::Size::BITS8);
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w.set_minc(vals::Inc::ENABLED);
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w.set_dir(dir);
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w.set_teie(true);
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w.set_tcie(true);
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w.set_en(true);
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});
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let res = poll_fn(|cx| {
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STATE.ch_wakers[state_number as usize].register(cx.waker());
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match STATE.ch_status[state_number as usize].load(Ordering::Acquire) {
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CH_STATUS_NONE => Poll::Pending,
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x => Poll::Ready(x),
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}
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})
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.await;
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on_drop.defuse();
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// TODO handle error
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assert!(res == CH_STATUS_COMPLETED);
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}
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macro_rules! dma_num {
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(DMA1) => {
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0
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};
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(DMA2) => {
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1
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};
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(BDMA) => {
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0
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};
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}
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unsafe fn on_irq() {
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pac::peripherals! {
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(bdma, $dma:ident) => {
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let isr = pac::$dma.isr().read();
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pac::$dma.ifcr().write_value(isr);
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let dman = dma_num!($dma);
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for chn in 0..crate::pac::dma_channels_count!($dma) {
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let n = dman * 8 + chn;
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if isr.teif(chn) {
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STATE.ch_status[n].store(CH_STATUS_ERROR, Ordering::Relaxed);
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STATE.ch_wakers[n].wake();
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} else if isr.tcif(chn) {
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STATE.ch_status[n].store(CH_STATUS_COMPLETED, Ordering::Relaxed);
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STATE.ch_wakers[n].wake();
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}
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}
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};
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}
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}
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/// safety: must be called only once
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pub(crate) unsafe fn init() {
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pac::interrupts! {
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(DMA, $irq:ident) => {
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crate::interrupt::$irq::steal().enable();
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};
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}
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pac::peripherals! {
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(bdma, $peri:ident) => {
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crate::peripherals::$peri::enable();
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};
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}
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}
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pac::bdma_channels! {
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($channel_peri:ident, $dma_peri:ident, $channel_num:expr) => {
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impl crate::dma::sealed::Channel for crate::peripherals::$channel_peri {}
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impl Channel for crate::peripherals::$channel_peri
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{
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type ReadFuture<'a> = impl Future<Output = ()>;
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type WriteFuture<'a> = impl Future<Output = ()>;
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fn read<'a>(
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&'a mut self,
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request: Request,
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src: *mut u8,
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buf: &'a mut [u8],
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) -> Self::ReadFuture<'a> {
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unsafe {
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do_transfer(
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crate::pac::$dma_peri,
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$channel_num,
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(dma_num!($dma_peri) * 8) + $channel_num,
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request,
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vals::Dir::FROMPERIPHERAL,
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src,
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buf.as_mut_ptr(),
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buf.len(),
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#[cfg(dmamux)]
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<Self as super::dmamux::MuxChannel>::DMAMUX_REGS,
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#[cfg(dmamux)]
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<Self as super::dmamux::MuxChannel>::DMAMUX_CH_NUM,
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)
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}
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}
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fn write<'a>(
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&'a mut self,
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request: Request,
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buf: &'a [u8],
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dst: *mut u8,
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) -> Self::WriteFuture<'a> {
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unsafe {
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do_transfer(
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crate::pac::$dma_peri,
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$channel_num,
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(dma_num!($dma_peri) * 8) + $channel_num,
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request,
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vals::Dir::FROMMEMORY,
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dst,
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buf.as_ptr() as *mut u8,
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buf.len(),
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#[cfg(dmamux)]
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<Self as super::dmamux::MuxChannel>::DMAMUX_REGS,
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#[cfg(dmamux)]
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<Self as super::dmamux::MuxChannel>::DMAMUX_CH_NUM,
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)
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}
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}
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}
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};
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}
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pac::interrupts! {
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(DMA, $irq:ident) => {
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#[crate::interrupt]
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unsafe fn $irq () {
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on_irq()
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}
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};
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}
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210
embassy-stm32/src/dma/dma.rs
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210
embassy-stm32/src/dma/dma.rs
Normal file
@ -0,0 +1,210 @@
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use core::task::Poll;
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use atomic_polyfill::{AtomicU8, Ordering};
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use core::future::Future;
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use embassy::interrupt::{Interrupt, InterruptExt};
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use embassy::util::AtomicWaker;
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use futures::future::poll_fn;
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use crate::interrupt;
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use crate::pac;
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use crate::pac::dma::{regs, vals};
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use crate::rcc::sealed::RccPeripheral;
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use super::{Channel, Request};
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const CH_COUNT: usize = pac::peripheral_count!(DMA) * 8;
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const CH_STATUS_NONE: u8 = 0;
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const CH_STATUS_COMPLETED: u8 = 1;
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const CH_STATUS_ERROR: u8 = 2;
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struct State {
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ch_wakers: [AtomicWaker; CH_COUNT],
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ch_status: [AtomicU8; CH_COUNT],
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}
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impl State {
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const fn new() -> Self {
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const AW: AtomicWaker = AtomicWaker::new();
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const AU: AtomicU8 = AtomicU8::new(CH_STATUS_NONE);
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Self {
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ch_wakers: [AW; CH_COUNT],
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ch_status: [AU; CH_COUNT],
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}
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}
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}
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static STATE: State = State::new();
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//async unsafe fn do_transfer(ch: &mut impl Channel, ch_func: u8, src: *const u8, dst: &mut [u8]) {
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pub(crate) async unsafe fn do_transfer(
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dma: pac::dma::Dma,
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channel_number: u8,
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state_number: u8,
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request: Request,
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dir: vals::Dir,
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peri_addr: *const u8,
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mem_addr: *mut u8,
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mem_len: usize,
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#[cfg(dmamux)] dmamux_regs: pac::dmamux::Dmamux,
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#[cfg(dmamux)] dmamux_ch_num: u8,
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) {
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// ndtr is max 16 bits.
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assert!(mem_len <= 0xFFFF);
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// Reset status
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// Generate a DMB here to flush the store buffer (M7) before enabling the DMA
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STATE.ch_status[state_number as usize].store(CH_STATUS_NONE, Ordering::Release);
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let ch = dma.st(channel_number as _);
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#[cfg(dmamux)]
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super::dmamux::configure_dmamux(dmamux_regs, dmamux_ch_num, request);
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unsafe {
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ch.par().write_value(peri_addr as u32);
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ch.m0ar().write_value(mem_addr as u32);
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ch.ndtr().write_value(regs::Ndtr(mem_len as _));
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ch.cr().write(|w| {
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w.set_dir(dir);
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w.set_msize(vals::Size::BITS8);
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w.set_psize(vals::Size::BITS8);
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w.set_minc(vals::Inc::INCREMENTED);
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w.set_pinc(vals::Inc::FIXED);
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w.set_teie(true);
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w.set_tcie(true);
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w.set_en(true);
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#[cfg(dma_v2)]
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w.set_chsel(request);
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});
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}
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let res = poll_fn(|cx| {
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let n = channel_number as usize;
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STATE.ch_wakers[n].register(cx.waker());
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match STATE.ch_status[n].load(Ordering::Acquire) {
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CH_STATUS_NONE => Poll::Pending,
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x => Poll::Ready(x),
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}
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})
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.await;
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// TODO handle error
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assert!(res == CH_STATUS_COMPLETED);
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}
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macro_rules! dma_num {
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(DMA1) => {
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0
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};
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(DMA2) => {
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1
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};
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}
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unsafe fn on_irq() {
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pac::peripherals! {
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(dma, $dma:ident) => {
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for isrn in 0..2 {
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let isr = pac::$dma.isr(isrn).read();
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pac::$dma.ifcr(isrn).write_value(isr);
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let dman = dma_num!($dma);
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for chn in 0..4 {
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let n = dman * 8 + isrn * 4 + chn;
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if isr.teif(chn) {
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STATE.ch_status[n].store(CH_STATUS_ERROR, Ordering::Relaxed);
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STATE.ch_wakers[n].wake();
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} else if isr.tcif(chn) {
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STATE.ch_status[n].store(CH_STATUS_COMPLETED, Ordering::Relaxed);
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STATE.ch_wakers[n].wake();
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}
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}
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}
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};
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}
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}
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/// safety: must be called only once
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pub(crate) unsafe fn init() {
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pac::interrupts! {
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(DMA, $irq:ident) => {
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interrupt::$irq::steal().enable();
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};
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}
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pac::peripherals! {
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(dma, $peri:ident) => {
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crate::peripherals::$peri::enable();
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};
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}
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}
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pac::dma_channels! {
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($channel_peri:ident, $dma_peri:ident, $channel_num:expr) => {
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impl crate::dma::sealed::Channel for crate::peripherals::$channel_peri {}
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impl Channel for crate::peripherals::$channel_peri
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{
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type ReadFuture<'a> = impl Future<Output = ()>;
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type WriteFuture<'a> = impl Future<Output = ()>;
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fn read<'a>(
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&'a mut self,
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request: Request,
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src: *mut u8,
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buf: &'a mut [u8],
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) -> Self::ReadFuture<'a> {
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unsafe {
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do_transfer(
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crate::pac::$dma_peri,
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$channel_num,
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(dma_num!($dma_peri) * 8) + $channel_num,
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request,
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vals::Dir::PERIPHERALTOMEMORY,
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src,
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buf.as_mut_ptr(),
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buf.len(),
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#[cfg(dmamux)]
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<Self as super::dmamux::MuxChannel>::DMAMUX_REGS,
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#[cfg(dmamux)]
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<Self as super::dmamux::MuxChannel>::DMAMUX_CH_NUM,
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)
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}
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}
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fn write<'a>(
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&'a mut self,
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request: Request,
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buf: &'a [u8],
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dst: *mut u8,
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) -> Self::WriteFuture<'a> {
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unsafe {
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do_transfer(
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crate::pac::$dma_peri,
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$channel_num,
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(dma_num!($dma_peri) * 8) + $channel_num,
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request,
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vals::Dir::MEMORYTOPERIPHERAL,
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dst,
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buf.as_ptr() as *mut u8,
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buf.len(),
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#[cfg(dmamux)]
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<Self as super::dmamux::MuxChannel>::DMAMUX_REGS,
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#[cfg(dmamux)]
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<Self as super::dmamux::MuxChannel>::DMAMUX_CH_NUM,
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)
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}
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}
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}
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};
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}
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pac::interrupts! {
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(DMA, $irq:ident) => {
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#[crate::interrupt]
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unsafe fn $irq () {
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on_irq()
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}
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};
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}
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61
embassy-stm32/src/dma/dmamux.rs
Normal file
61
embassy-stm32/src/dma/dmamux.rs
Normal file
@ -0,0 +1,61 @@
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#![macro_use]
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use crate::pac;
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use crate::peripherals;
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pub(crate) unsafe fn configure_dmamux(
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dmamux_regs: pac::dmamux::Dmamux,
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dmamux_ch_num: u8,
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request: u8,
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) {
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let ch_mux_regs = dmamux_regs.ccr(dmamux_ch_num as _);
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ch_mux_regs.write(|reg| {
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reg.set_nbreq(0);
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reg.set_dmareq_id(request);
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});
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ch_mux_regs.modify(|reg| {
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reg.set_ege(true);
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});
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}
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pub(crate) trait MuxChannel {
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const DMAMUX_CH_NUM: u8;
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const DMAMUX_REGS: pac::dmamux::Dmamux;
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}
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macro_rules! dma_num {
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(DMA1) => {
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0
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};
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(DMA2) => {
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1
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};
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(BDMA) => {
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0
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};
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}
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macro_rules! dmamux_peri {
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(DMA1) => {
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crate::pac::DMAMUX1
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};
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(DMA2) => {
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crate::pac::DMAMUX1
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};
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(BDMA) => {
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crate::pac::DMAMUX1
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};
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}
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pac::bdma_channels! {
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($channel_peri:ident, $dma_peri:ident, $channel_num:expr) => {
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impl MuxChannel for peripherals::$channel_peri {
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const DMAMUX_CH_NUM: u8 = (dma_num!($dma_peri) * 8) + $channel_num;
|
||||
const DMAMUX_REGS: pac::dmamux::Dmamux = dmamux_peri!($dma_peri);
|
||||
}
|
||||
};
|
||||
}
|
||||
|
||||
/// safety: must be called only once
|
||||
pub(crate) unsafe fn init() {}
|
||||
@ -1,9 +1,62 @@
|
||||
#![macro_use]
|
||||
|
||||
#[cfg_attr(dma_v1, path = "v1.rs")]
|
||||
#[cfg_attr(dma_v2, path = "v2.rs")]
|
||||
mod _version;
|
||||
|
||||
#[cfg(bdma)]
|
||||
mod bdma;
|
||||
#[cfg(dma)]
|
||||
#[allow(unused)]
|
||||
pub use _version::*;
|
||||
mod dma;
|
||||
#[cfg(dmamux)]
|
||||
mod dmamux;
|
||||
|
||||
use core::future::Future;
|
||||
use embassy::util::Unborrow;
|
||||
|
||||
#[cfg(any(bdma_v2, dma_v2, dmamux))]
|
||||
pub type Request = u8;
|
||||
#[cfg(not(any(bdma_v2, dma_v2, dmamux)))]
|
||||
pub type Request = ();
|
||||
|
||||
pub(crate) mod sealed {
|
||||
pub trait Channel {}
|
||||
}
|
||||
|
||||
pub trait Channel: sealed::Channel {
|
||||
type ReadFuture<'a>: Future<Output = ()> + 'a
|
||||
where
|
||||
Self: 'a;
|
||||
|
||||
type WriteFuture<'a>: Future<Output = ()> + 'a
|
||||
where
|
||||
Self: 'a;
|
||||
|
||||
fn read<'a>(
|
||||
&'a mut self,
|
||||
request: Request,
|
||||
src: *mut u8,
|
||||
buf: &'a mut [u8],
|
||||
) -> Self::ReadFuture<'a>;
|
||||
|
||||
fn write<'a>(
|
||||
&'a mut self,
|
||||
request: Request,
|
||||
buf: &'a [u8],
|
||||
dst: *mut u8,
|
||||
) -> Self::WriteFuture<'a>;
|
||||
}
|
||||
|
||||
pub struct NoDma;
|
||||
|
||||
unsafe impl Unborrow for NoDma {
|
||||
type Target = NoDma;
|
||||
|
||||
unsafe fn unborrow(self) -> Self::Target {
|
||||
self
|
||||
}
|
||||
}
|
||||
|
||||
// safety: must be called only once at startup
|
||||
pub(crate) unsafe fn init() {
|
||||
#[cfg(bdma)]
|
||||
bdma::init();
|
||||
#[cfg(dma)]
|
||||
dma::init();
|
||||
#[cfg(dmamux)]
|
||||
dmamux::init();
|
||||
}
|
||||
|
||||
@ -1,2 +0,0 @@
|
||||
/// safety: must be called only once
|
||||
pub(crate) unsafe fn init() {}
|
||||
@ -1,331 +0,0 @@
|
||||
use core::task::Poll;
|
||||
|
||||
use crate::dma_traits::{ReadDma, WriteDma};
|
||||
use atomic_polyfill::{AtomicU8, Ordering};
|
||||
use core::future::Future;
|
||||
use embassy::interrupt::{Interrupt, InterruptExt};
|
||||
use embassy::util::AtomicWaker;
|
||||
use futures::future::poll_fn;
|
||||
|
||||
use crate::interrupt;
|
||||
use crate::pac;
|
||||
use crate::pac::dma::{regs, vals};
|
||||
|
||||
use crate::pac::dma_channels;
|
||||
use crate::pac::interrupts;
|
||||
use crate::pac::peripheral_count;
|
||||
use crate::pac::peripheral_dma_channels;
|
||||
use crate::pac::peripherals;
|
||||
use crate::peripherals;
|
||||
|
||||
const CH_COUNT: usize = peripheral_count!(DMA) * 8;
|
||||
const CH_STATUS_NONE: u8 = 0;
|
||||
const CH_STATUS_COMPLETED: u8 = 1;
|
||||
const CH_STATUS_ERROR: u8 = 2;
|
||||
|
||||
struct State {
|
||||
ch_wakers: [AtomicWaker; CH_COUNT],
|
||||
ch_status: [AtomicU8; CH_COUNT],
|
||||
}
|
||||
|
||||
impl State {
|
||||
const fn new() -> Self {
|
||||
const AW: AtomicWaker = AtomicWaker::new();
|
||||
const AU: AtomicU8 = AtomicU8::new(CH_STATUS_NONE);
|
||||
Self {
|
||||
ch_wakers: [AW; CH_COUNT],
|
||||
ch_status: [AU; CH_COUNT],
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static STATE: State = State::new();
|
||||
|
||||
#[allow(unused)] // Used by usart/v1.rs which may or may not be enabled
|
||||
pub(crate) async unsafe fn transfer_p2m(
|
||||
ch: &mut impl Channel,
|
||||
ch_func: u8,
|
||||
src: *const u8,
|
||||
dst: &mut [u8],
|
||||
) {
|
||||
let n = ch.num();
|
||||
let c = ch.regs();
|
||||
|
||||
// ndtr is max 16 bits.
|
||||
assert!(dst.len() <= 0xFFFF);
|
||||
|
||||
// Reset status
|
||||
// Generate a DMB here to flush the store buffer (M7) before enabling the DMA
|
||||
STATE.ch_status[n].store(CH_STATUS_NONE, Ordering::Release);
|
||||
|
||||
unsafe {
|
||||
c.par().write_value(src as _);
|
||||
c.m0ar().write_value(dst.as_ptr() as _);
|
||||
c.ndtr().write_value(regs::Ndtr(dst.len() as _));
|
||||
c.cr().write(|w| {
|
||||
w.set_dir(vals::Dir::PERIPHERALTOMEMORY);
|
||||
w.set_msize(vals::Size::BITS8);
|
||||
w.set_psize(vals::Size::BITS8);
|
||||
w.set_minc(vals::Inc::INCREMENTED);
|
||||
w.set_pinc(vals::Inc::FIXED);
|
||||
w.set_chsel(ch_func);
|
||||
w.set_teie(true);
|
||||
w.set_tcie(true);
|
||||
w.set_en(true);
|
||||
});
|
||||
}
|
||||
|
||||
let res = poll_fn(|cx| {
|
||||
STATE.ch_wakers[n].register(cx.waker());
|
||||
match STATE.ch_status[n].load(Ordering::Acquire) {
|
||||
CH_STATUS_NONE => Poll::Pending,
|
||||
x => Poll::Ready(x),
|
||||
}
|
||||
})
|
||||
.await;
|
||||
|
||||
// TODO handle error
|
||||
assert!(res == CH_STATUS_COMPLETED);
|
||||
}
|
||||
|
||||
#[allow(unused)] // Used by usart/v1.rs which may or may not be enabled
|
||||
pub(crate) async unsafe fn transfer_m2p(
|
||||
ch: &mut impl Channel,
|
||||
ch_func: u8,
|
||||
src: &[u8],
|
||||
dst: *mut u8,
|
||||
) {
|
||||
let n = ch.num();
|
||||
let c = ch.regs();
|
||||
|
||||
// ndtr is max 16 bits.
|
||||
assert!(src.len() <= 0xFFFF);
|
||||
|
||||
// Reset status
|
||||
// Generate a DMB here to flush the store buffer (M7) before enabling the DMA
|
||||
STATE.ch_status[n].store(CH_STATUS_NONE, Ordering::Release);
|
||||
|
||||
unsafe {
|
||||
c.par().write_value(dst as _);
|
||||
c.m0ar().write_value(src.as_ptr() as _);
|
||||
c.ndtr().write_value(regs::Ndtr(src.len() as _));
|
||||
c.cr().write(|w| {
|
||||
w.set_dir(vals::Dir::MEMORYTOPERIPHERAL);
|
||||
w.set_msize(vals::Size::BITS8);
|
||||
w.set_psize(vals::Size::BITS8);
|
||||
w.set_minc(vals::Inc::INCREMENTED);
|
||||
w.set_pinc(vals::Inc::FIXED);
|
||||
w.set_chsel(ch_func);
|
||||
w.set_teie(true);
|
||||
w.set_tcie(true);
|
||||
w.set_en(true);
|
||||
});
|
||||
}
|
||||
|
||||
let res = poll_fn(|cx| {
|
||||
STATE.ch_wakers[n].register(cx.waker());
|
||||
match STATE.ch_status[n].load(Ordering::Acquire) {
|
||||
CH_STATUS_NONE => {
|
||||
let left = c.ndtr().read().ndt();
|
||||
Poll::Pending
|
||||
}
|
||||
x => Poll::Ready(x),
|
||||
}
|
||||
})
|
||||
.await;
|
||||
|
||||
// TODO handle error
|
||||
assert!(res == CH_STATUS_COMPLETED);
|
||||
}
|
||||
|
||||
unsafe fn on_irq() {
|
||||
peripherals! {
|
||||
(dma, $dma:ident) => {
|
||||
for isrn in 0..2 {
|
||||
let isr = pac::$dma.isr(isrn).read();
|
||||
pac::$dma.ifcr(isrn).write_value(isr);
|
||||
let dman = <peripherals::$dma as sealed::Dma>::num() as usize;
|
||||
|
||||
for chn in 0..4 {
|
||||
let n = dman * 8 + isrn * 4 + chn;
|
||||
if isr.teif(chn) {
|
||||
STATE.ch_status[n].store(CH_STATUS_ERROR, Ordering::Relaxed);
|
||||
STATE.ch_wakers[n].wake();
|
||||
} else if isr.tcif(chn) {
|
||||
STATE.ch_status[n].store(CH_STATUS_COMPLETED, Ordering::Relaxed);
|
||||
STATE.ch_wakers[n].wake();
|
||||
}
|
||||
}
|
||||
}
|
||||
};
|
||||
}
|
||||
}
|
||||
|
||||
/// safety: must be called only once
|
||||
pub(crate) unsafe fn init() {
|
||||
interrupts! {
|
||||
(DMA, $irq:ident) => {
|
||||
interrupt::$irq::steal().enable();
|
||||
};
|
||||
}
|
||||
}
|
||||
|
||||
pub(crate) mod sealed {
|
||||
use super::*;
|
||||
|
||||
pub trait Dma {
|
||||
fn num() -> u8;
|
||||
fn regs() -> &'static pac::dma::Dma;
|
||||
}
|
||||
|
||||
pub trait Channel {
|
||||
fn dma_regs() -> &'static pac::dma::Dma;
|
||||
|
||||
fn num(&self) -> usize;
|
||||
|
||||
fn ch_num(&self) -> u8;
|
||||
|
||||
fn regs(&self) -> pac::dma::St {
|
||||
Self::dma_regs().st(self.ch_num() as _)
|
||||
}
|
||||
}
|
||||
|
||||
pub trait PeripheralChannel<PERI, OP>: Channel {
|
||||
fn request(&self) -> u8;
|
||||
}
|
||||
}
|
||||
|
||||
pub trait Dma: sealed::Dma + Sized {}
|
||||
pub trait Channel: sealed::Channel + Sized {}
|
||||
pub trait PeripheralChannel<PERI, OP>: sealed::PeripheralChannel<PERI, OP> + Sized {}
|
||||
|
||||
macro_rules! impl_dma {
|
||||
($peri:ident, $num:expr) => {
|
||||
impl Dma for peripherals::$peri {}
|
||||
impl sealed::Dma for peripherals::$peri {
|
||||
fn num() -> u8 {
|
||||
$num
|
||||
}
|
||||
fn regs() -> &'static pac::dma::Dma {
|
||||
&pac::$peri
|
||||
}
|
||||
}
|
||||
};
|
||||
}
|
||||
|
||||
macro_rules! impl_dma_channel {
|
||||
($channel_peri:ident, $dma_peri:ident, $dma_num:expr, $ch_num:expr) => {
|
||||
impl Channel for peripherals::$channel_peri {}
|
||||
impl sealed::Channel for peripherals::$channel_peri {
|
||||
#[inline]
|
||||
fn dma_regs() -> &'static pac::dma::Dma {
|
||||
&crate::pac::$dma_peri
|
||||
}
|
||||
|
||||
fn num(&self) -> usize {
|
||||
($dma_num * 8) + $ch_num
|
||||
}
|
||||
|
||||
fn ch_num(&self) -> u8 {
|
||||
$ch_num
|
||||
}
|
||||
}
|
||||
|
||||
impl<T> WriteDma<T> for peripherals::$channel_peri
|
||||
where
|
||||
Self: sealed::PeripheralChannel<T, M2P>,
|
||||
T: 'static,
|
||||
{
|
||||
type WriteDmaFuture<'a> = impl Future<Output = ()>;
|
||||
|
||||
fn transfer<'a>(&'a mut self, buf: &'a [u8], dst: *mut u8) -> Self::WriteDmaFuture<'a>
|
||||
where
|
||||
T: 'a,
|
||||
{
|
||||
let request = sealed::PeripheralChannel::<T, M2P>::request(self);
|
||||
unsafe { transfer_m2p(self, request, buf, dst) }
|
||||
}
|
||||
}
|
||||
|
||||
impl<T> ReadDma<T> for peripherals::$channel_peri
|
||||
where
|
||||
Self: sealed::PeripheralChannel<T, P2M>,
|
||||
T: 'static,
|
||||
{
|
||||
type ReadDmaFuture<'a> = impl Future<Output = ()>;
|
||||
|
||||
fn transfer<'a>(
|
||||
&'a mut self,
|
||||
src: *const u8,
|
||||
buf: &'a mut [u8],
|
||||
) -> Self::ReadDmaFuture<'a>
|
||||
where
|
||||
T: 'a,
|
||||
{
|
||||
let request = sealed::PeripheralChannel::<T, P2M>::request(self);
|
||||
unsafe { transfer_p2m(self, request, src, buf) }
|
||||
}
|
||||
}
|
||||
};
|
||||
}
|
||||
|
||||
peripherals! {
|
||||
(dma, DMA1) => {
|
||||
impl_dma!(DMA1, 0);
|
||||
dma_channels! {
|
||||
($channel_peri:ident, DMA1, $channel_num:expr) => {
|
||||
impl_dma_channel!($channel_peri, DMA1, 0, $channel_num);
|
||||
};
|
||||
}
|
||||
};
|
||||
(dma, DMA2) => {
|
||||
impl_dma!(DMA2, 1);
|
||||
dma_channels! {
|
||||
($channel_peri:ident, DMA2, $channel_num:expr) => {
|
||||
impl_dma_channel!($channel_peri, DMA2, 1, $channel_num);
|
||||
};
|
||||
}
|
||||
};
|
||||
}
|
||||
|
||||
interrupts! {
|
||||
(DMA, $irq:ident) => {
|
||||
#[crate::interrupt]
|
||||
unsafe fn $irq () {
|
||||
on_irq()
|
||||
}
|
||||
};
|
||||
}
|
||||
|
||||
pub struct P2M;
|
||||
pub struct M2P;
|
||||
|
||||
#[cfg(usart)]
|
||||
use crate::usart;
|
||||
peripheral_dma_channels! {
|
||||
($peri:ident, usart, $kind:ident, RX, $channel_peri:ident, $dma_peri:ident, $channel_num:expr, $event_num:expr) => {
|
||||
impl usart::RxDma<peripherals::$peri> for peripherals::$channel_peri { }
|
||||
impl usart::sealed::RxDma<peripherals::$peri> for peripherals::$channel_peri { }
|
||||
|
||||
impl sealed::PeripheralChannel<peripherals::$peri, P2M> for peripherals::$channel_peri {
|
||||
fn request(&self) -> u8 {
|
||||
$event_num
|
||||
}
|
||||
}
|
||||
|
||||
impl PeripheralChannel<peripherals::$peri, P2M> for peripherals::$channel_peri { }
|
||||
};
|
||||
|
||||
($peri:ident, usart, $kind:ident, TX, $channel_peri:ident, $dma_peri:ident, $channel_num:expr, $event_num:expr) => {
|
||||
impl usart::TxDma<peripherals::$peri> for peripherals::$channel_peri { }
|
||||
impl usart::sealed::TxDma<peripherals::$peri> for peripherals::$channel_peri { }
|
||||
|
||||
impl sealed::PeripheralChannel<peripherals::$peri, M2P> for peripherals::$channel_peri {
|
||||
fn request(&self) -> u8 {
|
||||
$event_num
|
||||
}
|
||||
}
|
||||
|
||||
impl PeripheralChannel<peripherals::$peri, M2P> for peripherals::$channel_peri { }
|
||||
};
|
||||
}
|
||||
Reference in New Issue
Block a user