Merge pull request #207 from lulf/clock-init
Enable clock by default for stm32l0
This commit is contained in:
Dario Nieuwenhuis
GitHub
commit
3f6f1d99bb
@ -7,20 +7,21 @@ pub fn generate(embassy_prefix: &ModulePrefix, config: syn::Expr) -> TokenStream
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let embassy_stm32_path = embassy_prefix.append("embassy_stm32").path();
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quote!(
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use #embassy_stm32_path::{clock::Clock};
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use #embassy_stm32_path::{interrupt, peripherals, clock::Clock, time::Hertz};
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let p = #embassy_stm32_path::init(#config);
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/*
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let mut rtc = #embass::RTC::new(unsafe { <peripherals::TIM2 as #embassy_path::util::Steal>::steal() }, interrupt::take!(TIM2));
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let rtc = unsafe { make_static(&mut rtc) };
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rtc.start();
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let mut alarm = rtc.alarm0();
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let mut c = Clock::new(
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unsafe { <peripherals::TIM2 as embassy::util::Steal>::steal() },
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interrupt::take!(TIM2),
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);
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let clock = unsafe { make_static(&mut c) };
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clock.start_tim2();
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unsafe { #embassy_path::time::set_clock(rtc) };
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let mut alarm = clock.alarm1();
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unsafe { #embassy_path::time::set_clock(clock) };
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let alarm = unsafe { make_static(&mut alarm) };
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executor.set_alarm(alarm);
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*/
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)
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}
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@ -10,6 +10,7 @@ use embassy::time::{Clock as EmbassyClock, TICKS_PER_SECOND};
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use crate::interrupt::{CriticalSection, Interrupt, Mutex};
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use crate::pac::timer::TimGp16;
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use crate::rcc::get_freqs;
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use crate::time::Hertz;
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// Clock timekeeping works with something we call "periods", which are time intervals
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@ -75,6 +76,24 @@ impl<T: Instance> Clock<T> {
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}
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}
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// TODO: Temporary until clock code generation is in place
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pub fn start_tim2(&'static self) {
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cfg_if::cfg_if! {
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if #[cfg(feature = "_stm32l0")] {
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unsafe {
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let rcc = crate::pac::RCC;
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rcc.apb1enr()
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.modify(|w| w.set_tim2en(crate::pac::rcc::vals::Lptimen::ENABLED));
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rcc.apb1rstr().modify(|w| w.set_tim2rst(true));
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rcc.apb1rstr().modify(|w| w.set_tim2rst(false));
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}
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let timer_freq = unsafe { crate::rcc::get_freqs().apb1_clk };
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self.start(timer_freq);
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}
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}
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}
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pub fn start(&'static self, timer_freq: Hertz) {
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let inner = T::inner();
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@ -47,6 +47,13 @@ pub struct Config {
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rcc: rcc::Config,
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}
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impl Config {
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pub fn rcc(mut self, rcc: rcc::Config) -> Self {
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self.rcc = rcc;
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self
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}
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}
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impl Default for Config {
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fn default() -> Self {
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Self {
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@ -528,6 +528,5 @@ impl<'d> Rcc<'d> {
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}
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}
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pub unsafe fn init(config: Config) {
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// TODO
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}
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pub unsafe fn init(_config: Config) {}
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@ -1,13 +1,484 @@
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use crate::pac;
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use embassy::util::Steal;
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use pac::rcc::{self, vals};
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use crate::pac::peripherals::{self, RCC};
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use crate::rcc::{set_freqs, Clocks};
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use crate::time::Hertz;
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use crate::time::U32Ext;
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use embassy::util::Unborrow;
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use pac::rcc::vals;
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use vals::{Hpre, Msirange, Plldiv, Pllmul, Pllon, Pllsrc, Ppre, Sw};
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#[derive(Default)]
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pub struct Config {}
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/// Most of clock setup is copied from stm32l0xx-hal, and adopted to the generated PAC,
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/// and with the addition of the init function to configure a system clock.
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/// System clock mux source
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#[derive(Clone, Copy)]
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pub enum ClockSrc {
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MSI(MSIRange),
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PLL(PLLSource, PLLMul, PLLDiv),
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HSE(Hertz),
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HSI16,
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}
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/// MSI Clock Range
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///
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/// These ranges control the frequency of the MSI. Internally, these ranges map
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/// to the `MSIRANGE` bits in the `RCC_ICSCR` register.
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#[derive(Clone, Copy)]
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pub enum MSIRange {
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/// Around 65.536 kHz
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Range0,
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/// Around 131.072 kHz
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Range1,
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/// Around 262.144 kHz
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Range2,
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/// Around 524.288 kHz
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Range3,
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/// Around 1.048 MHz
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Range4,
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/// Around 2.097 MHz (reset value)
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Range5,
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/// Around 4.194 MHz
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Range6,
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}
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impl Default for MSIRange {
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fn default() -> MSIRange {
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MSIRange::Range5
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}
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}
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/// PLL divider
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#[derive(Clone, Copy)]
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pub enum PLLDiv {
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Div2,
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Div3,
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Div4,
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}
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/// PLL multiplier
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#[derive(Clone, Copy)]
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pub enum PLLMul {
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Mul3,
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Mul4,
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Mul6,
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Mul8,
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Mul12,
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Mul16,
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Mul24,
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Mul32,
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Mul48,
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}
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/// AHB prescaler
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#[derive(Clone, Copy)]
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pub enum AHBPrescaler {
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NotDivided,
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Div2,
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Div4,
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Div8,
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Div16,
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Div64,
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Div128,
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Div256,
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Div512,
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}
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/// APB prescaler
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#[derive(Clone, Copy)]
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pub enum APBPrescaler {
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NotDivided,
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Div2,
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Div4,
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Div8,
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Div16,
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}
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/// PLL clock input source
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#[derive(Clone, Copy)]
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pub enum PLLSource {
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HSI16,
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HSE(Hertz),
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}
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/// HSI speed
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pub const HSI_FREQ: u32 = 16_000_000;
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impl Into<Pllmul> for PLLMul {
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fn into(self) -> Pllmul {
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match self {
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PLLMul::Mul3 => Pllmul::MUL3,
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PLLMul::Mul4 => Pllmul::MUL4,
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PLLMul::Mul6 => Pllmul::MUL6,
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PLLMul::Mul8 => Pllmul::MUL8,
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PLLMul::Mul12 => Pllmul::MUL12,
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PLLMul::Mul16 => Pllmul::MUL16,
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PLLMul::Mul24 => Pllmul::MUL24,
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PLLMul::Mul32 => Pllmul::MUL32,
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PLLMul::Mul48 => Pllmul::MUL48,
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}
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}
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}
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impl Into<Plldiv> for PLLDiv {
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fn into(self) -> Plldiv {
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match self {
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PLLDiv::Div2 => Plldiv::DIV2,
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PLLDiv::Div3 => Plldiv::DIV3,
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PLLDiv::Div4 => Plldiv::DIV4,
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}
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}
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}
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impl Into<Pllsrc> for PLLSource {
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fn into(self) -> Pllsrc {
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match self {
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PLLSource::HSI16 => Pllsrc::HSI16,
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PLLSource::HSE(_) => Pllsrc::HSE,
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}
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}
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}
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impl Into<Ppre> for APBPrescaler {
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fn into(self) -> Ppre {
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match self {
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APBPrescaler::NotDivided => Ppre::DIV1,
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APBPrescaler::Div2 => Ppre::DIV2,
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APBPrescaler::Div4 => Ppre::DIV4,
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APBPrescaler::Div8 => Ppre::DIV8,
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APBPrescaler::Div16 => Ppre::DIV16,
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}
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}
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}
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impl Into<Hpre> for AHBPrescaler {
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fn into(self) -> Hpre {
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match self {
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AHBPrescaler::NotDivided => Hpre::DIV1,
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AHBPrescaler::Div2 => Hpre::DIV2,
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AHBPrescaler::Div4 => Hpre::DIV4,
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AHBPrescaler::Div8 => Hpre::DIV8,
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AHBPrescaler::Div16 => Hpre::DIV16,
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AHBPrescaler::Div64 => Hpre::DIV64,
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AHBPrescaler::Div128 => Hpre::DIV128,
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AHBPrescaler::Div256 => Hpre::DIV256,
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AHBPrescaler::Div512 => Hpre::DIV512,
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}
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}
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}
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impl Into<Msirange> for MSIRange {
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fn into(self) -> Msirange {
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match self {
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MSIRange::Range0 => Msirange::RANGE0,
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MSIRange::Range1 => Msirange::RANGE1,
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MSIRange::Range2 => Msirange::RANGE2,
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MSIRange::Range3 => Msirange::RANGE3,
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MSIRange::Range4 => Msirange::RANGE4,
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MSIRange::Range5 => Msirange::RANGE5,
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MSIRange::Range6 => Msirange::RANGE6,
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}
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}
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}
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/// Clocks configutation
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pub struct Config {
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mux: ClockSrc,
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ahb_pre: AHBPrescaler,
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apb1_pre: APBPrescaler,
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apb2_pre: APBPrescaler,
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}
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impl Default for Config {
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#[inline]
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fn default() -> Config {
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Config {
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mux: ClockSrc::MSI(MSIRange::default()),
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ahb_pre: AHBPrescaler::NotDivided,
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apb1_pre: APBPrescaler::NotDivided,
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apb2_pre: APBPrescaler::NotDivided,
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}
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}
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}
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impl Config {
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#[inline]
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pub fn clock_src(mut self, mux: ClockSrc) -> Self {
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self.mux = mux;
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self
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}
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#[inline]
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pub fn ahb_pre(mut self, pre: AHBPrescaler) -> Self {
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self.ahb_pre = pre;
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self
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}
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#[inline]
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pub fn apb1_pre(mut self, pre: APBPrescaler) -> Self {
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self.apb1_pre = pre;
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self
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}
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#[inline]
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pub fn apb2_pre(mut self, pre: APBPrescaler) -> Self {
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self.apb2_pre = pre;
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self
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}
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}
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/// RCC peripheral
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pub struct Rcc {}
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impl Rcc {
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pub fn new(_rcc: impl Unborrow<Target = peripherals::RCC> + 'static) -> Self {
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Self {}
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}
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}
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/*
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pub fn enable_lse(&mut self, _: &PWR) -> LSE {
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self.rb.csr.modify(|_, w| {
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// Enable LSE clock
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w.lseon().set_bit()
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});
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while self.rb.csr.read().lserdy().bit_is_clear() {}
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LSE(())
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}
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}
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impl Rcc {
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pub fn enable_hsi48(&mut self, syscfg: &mut SYSCFG, crs: CRS) -> HSI48 {
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// Reset CRS peripheral
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self.rb.apb1rstr.modify(|_, w| w.crsrst().set_bit());
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self.rb.apb1rstr.modify(|_, w| w.crsrst().clear_bit());
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// Enable CRS peripheral
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self.rb.apb1enr.modify(|_, w| w.crsen().set_bit());
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// Initialize CRS
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crs.cfgr.write(|w|
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// Select LSE as synchronization source
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unsafe { w.syncsrc().bits(0b01) });
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crs.cr
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.modify(|_, w| w.autotrimen().set_bit().cen().set_bit());
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// Enable VREFINT reference for HSI48 oscillator
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syscfg
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.syscfg
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.cfgr3
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.modify(|_, w| w.enref_hsi48().set_bit().en_vrefint().set_bit());
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// Select HSI48 as USB clock
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self.rb.ccipr.modify(|_, w| w.hsi48msel().set_bit());
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// Enable dedicated USB clock
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self.rb.crrcr.modify(|_, w| w.hsi48on().set_bit());
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while self.rb.crrcr.read().hsi48rdy().bit_is_clear() {}
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HSI48(())
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}
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}
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impl Rcc {
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/// Configure MCO (Microcontroller Clock Output).
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pub fn configure_mco<P>(
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&mut self,
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source: MCOSEL_A,
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prescaler: MCOPRE_A,
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output_pin: P,
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) -> MCOEnabled
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where
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P: mco::Pin,
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{
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output_pin.into_mco();
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self.rb.cfgr.modify(|_, w| {
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w.mcosel().variant(source);
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w.mcopre().variant(prescaler)
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});
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MCOEnabled(())
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}
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}
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*/
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/// Extension trait that freezes the `RCC` peripheral with provided clocks configuration
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pub trait RccExt {
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fn freeze(self, config: Config) -> Clocks;
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}
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impl RccExt for RCC {
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// `cfgr` is almost always a constant, so make sure it can be constant-propagated properly by
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// marking this function and all `Config` constructors and setters as `#[inline]`.
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// This saves ~900 Bytes for the `pwr.rs` example.
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#[inline]
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fn freeze(self, cfgr: Config) -> Clocks {
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let rcc = pac::RCC;
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let (sys_clk, sw) = match cfgr.mux {
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ClockSrc::MSI(range) => {
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// Set MSI range
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unsafe {
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rcc.icscr().write(|w| w.set_msirange(range.into()));
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}
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// Enable MSI
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unsafe {
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rcc.cr().write(|w| w.set_msion(Pllon::ENABLED));
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while !rcc.cr().read().msirdy() {}
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}
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let freq = 32_768 * (1 << (range as u8 + 1));
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(freq, Sw::MSI)
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}
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ClockSrc::HSI16 => {
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// Enable HSI16
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unsafe {
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rcc.cr().write(|w| w.set_hsi16on(Pllon::ENABLED));
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while !rcc.cr().read().hsi16rdyf() {}
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}
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(HSI_FREQ, Sw::HSI16)
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}
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ClockSrc::HSE(freq) => {
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// Enable HSE
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unsafe {
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rcc.cr().write(|w| w.set_hseon(Pllon::ENABLED));
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while !rcc.cr().read().hserdy() {}
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}
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(freq.0, Sw::HSE)
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}
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ClockSrc::PLL(src, mul, div) => {
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let freq = match src {
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PLLSource::HSE(freq) => {
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// Enable HSE
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unsafe {
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rcc.cr().write(|w| w.set_hseon(Pllon::ENABLED));
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while !rcc.cr().read().hserdy() {}
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}
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freq.0
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}
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PLLSource::HSI16 => {
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// Enable HSI
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unsafe {
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rcc.cr().write(|w| w.set_hsi16on(Pllon::ENABLED));
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while !rcc.cr().read().hsi16rdyf() {}
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}
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HSI_FREQ
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}
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};
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// Disable PLL
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unsafe {
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rcc.cr().modify(|w| w.set_pllon(Pllon::DISABLED));
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while rcc.cr().read().pllrdy() {}
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}
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let freq = match mul {
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PLLMul::Mul3 => freq * 3,
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PLLMul::Mul4 => freq * 4,
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PLLMul::Mul6 => freq * 6,
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PLLMul::Mul8 => freq * 8,
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PLLMul::Mul12 => freq * 12,
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PLLMul::Mul16 => freq * 16,
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PLLMul::Mul24 => freq * 24,
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PLLMul::Mul32 => freq * 32,
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PLLMul::Mul48 => freq * 48,
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};
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let freq = match div {
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PLLDiv::Div2 => freq / 2,
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PLLDiv::Div3 => freq / 3,
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PLLDiv::Div4 => freq / 4,
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};
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assert!(freq <= 32_u32.mhz().0);
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unsafe {
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rcc.cfgr().write(move |w| {
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w.set_pllmul(mul.into());
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w.set_plldiv(div.into());
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w.set_pllsrc(src.into());
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});
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// Enable PLL
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rcc.cr().modify(|w| w.set_pllon(Pllon::ENABLED));
|
||||
while !rcc.cr().read().pllrdy() {}
|
||||
}
|
||||
|
||||
(freq, Sw::PLL)
|
||||
}
|
||||
};
|
||||
|
||||
unsafe {
|
||||
rcc.cfgr().modify(|w| {
|
||||
w.set_sw(sw.into());
|
||||
w.set_hpre(cfgr.ahb_pre.into());
|
||||
w.set_ppre(0, cfgr.apb1_pre.into());
|
||||
w.set_ppre(1, cfgr.apb2_pre.into());
|
||||
});
|
||||
}
|
||||
|
||||
let ahb_freq: u32 = match cfgr.ahb_pre {
|
||||
AHBPrescaler::NotDivided => sys_clk,
|
||||
pre => {
|
||||
let pre: Hpre = pre.into();
|
||||
let pre = 1 << (pre.0 as u32 - 7);
|
||||
sys_clk / pre
|
||||
}
|
||||
};
|
||||
|
||||
let (apb1_freq, apb1_tim_freq, apb1_pre) = match cfgr.apb1_pre {
|
||||
APBPrescaler::NotDivided => (ahb_freq, ahb_freq, 1),
|
||||
pre => {
|
||||
let pre: Ppre = pre.into();
|
||||
let pre: u8 = 1 << (pre.0 - 3);
|
||||
let freq = ahb_freq / pre as u32;
|
||||
(freq, freq * 2, pre as u8)
|
||||
}
|
||||
};
|
||||
|
||||
let (apb2_freq, apb2_tim_freq, apb2_pre) = match cfgr.apb2_pre {
|
||||
APBPrescaler::NotDivided => (ahb_freq, ahb_freq, 1),
|
||||
pre => {
|
||||
let pre: Ppre = pre.into();
|
||||
let pre: u8 = 1 << (pre.0 - 3);
|
||||
let freq = ahb_freq / (1 << (pre as u8 - 3));
|
||||
(freq, freq * 2, pre as u8)
|
||||
}
|
||||
};
|
||||
|
||||
Clocks {
|
||||
sys_clk: sys_clk.hz(),
|
||||
ahb_clk: ahb_freq.hz(),
|
||||
apb1_clk: apb1_freq.hz(),
|
||||
apb2_clk: apb2_freq.hz(),
|
||||
apb1_tim_clk: apb1_tim_freq.hz(),
|
||||
apb2_tim_clk: apb2_tim_freq.hz(),
|
||||
apb1_pre,
|
||||
apb2_pre,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// Token that exists only, if the HSI48 clock has been enabled
|
||||
///
|
||||
/// You can get an instance of this struct by calling [`Rcc::enable_hsi48`].
|
||||
#[derive(Clone, Copy)]
|
||||
pub struct HSI48(());
|
||||
|
||||
/// Token that exists only if MCO (Microcontroller Clock Out) has been enabled.
|
||||
///
|
||||
/// You can get an instance of this struct by calling [`Rcc::configure_mco`].
|
||||
#[derive(Clone, Copy)]
|
||||
pub struct MCOEnabled(());
|
||||
|
||||
/// Token that exists only, if the LSE clock has been enabled
|
||||
///
|
||||
/// You can get an instance of this struct by calling [`Rcc::enable_lse`].
|
||||
#[derive(Clone, Copy)]
|
||||
pub struct LSE(());
|
||||
|
||||
pub unsafe fn init(config: Config) {
|
||||
let rcc = pac::RCC;
|
||||
|
||||
let enabled = vals::Iophen::ENABLED;
|
||||
rcc.iopenr().write(|w| {
|
||||
w.set_iopaen(enabled);
|
||||
@ -17,4 +488,8 @@ pub unsafe fn init(config: Config) {
|
||||
w.set_iopeen(enabled);
|
||||
w.set_iophen(enabled);
|
||||
});
|
||||
|
||||
let r = <peripherals::RCC as embassy::util::Steal>::steal();
|
||||
let clocks = r.freeze(config);
|
||||
set_freqs(clocks);
|
||||
}
|
||||
|
||||
@ -1,3 +1,35 @@
|
||||
use crate::time::Hertz;
|
||||
use core::mem::MaybeUninit;
|
||||
|
||||
/// Frozen clock frequencies
|
||||
///
|
||||
/// The existence of this value indicates that the clock configuration can no longer be changed
|
||||
#[derive(Clone, Copy)]
|
||||
pub struct Clocks {
|
||||
pub sys_clk: Hertz,
|
||||
pub ahb_clk: Hertz,
|
||||
pub apb1_clk: Hertz,
|
||||
pub apb1_tim_clk: Hertz,
|
||||
pub apb2_clk: Hertz,
|
||||
pub apb2_tim_clk: Hertz,
|
||||
pub apb1_pre: u8,
|
||||
pub apb2_pre: u8,
|
||||
}
|
||||
|
||||
static mut CLOCK_FREQS: MaybeUninit<Clocks> = MaybeUninit::uninit();
|
||||
|
||||
/// Sets the clock frequencies
|
||||
///
|
||||
/// Safety: Sets a mutable global.
|
||||
pub unsafe fn set_freqs(freqs: Clocks) {
|
||||
CLOCK_FREQS.as_mut_ptr().write(freqs);
|
||||
}
|
||||
|
||||
/// Safety: Reads a mutable global.
|
||||
pub unsafe fn get_freqs() -> &'static Clocks {
|
||||
&*CLOCK_FREQS.as_ptr()
|
||||
}
|
||||
|
||||
cfg_if::cfg_if! {
|
||||
if #[cfg(feature = "_stm32h7")] {
|
||||
mod h7;
|
||||
@ -8,6 +40,7 @@ cfg_if::cfg_if! {
|
||||
} else {
|
||||
#[derive(Default)]
|
||||
pub struct Config {}
|
||||
pub fn init(_config: Config) {}
|
||||
pub unsafe fn init(_config: Config) {
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user