From 3fce6ec649953fac52b731ea0aa7587ed60e55c9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Henrik=20Alse=CC=81r?= Date: Wed, 31 Aug 2022 21:54:42 +0200 Subject: [PATCH] Rearrange new:s --- embassy-rp/src/spi.rs | 176 ++++++++++++++++++++++++++--------------- embassy-rp/src/uart.rs | 16 +++- 2 files changed, 128 insertions(+), 64 deletions(-) diff --git a/embassy-rp/src/spi.rs b/embassy-rp/src/spi.rs index 720aad0e..9bf6a911 100644 --- a/embassy-rp/src/spi.rs +++ b/embassy-rp/src/spi.rs @@ -65,66 +65,6 @@ fn calc_prescs(freq: u32) -> (u8, u8) { } impl<'d, T: Instance, M: Mode> Spi<'d, T, M> { - pub fn new_blocking( - inner: impl Peripheral

+ 'd, - clk: impl Peripheral

+ 'd> + 'd, - mosi: impl Peripheral

+ 'd> + 'd, - miso: impl Peripheral

+ 'd> + 'd, - config: Config, - ) -> Self { - into_ref!(clk, mosi, miso); - Self::new_inner( - inner, - None, - None, - Some(clk.map_into()), - Some(mosi.map_into()), - Some(miso.map_into()), - None, - config, - ) - } - - pub fn new_txonly( - inner: impl Peripheral

+ 'd, - tx_dma: Option>, - clk: impl Peripheral

+ 'd> + 'd, - mosi: impl Peripheral

+ 'd> + 'd, - config: Config, - ) -> Self { - into_ref!(clk, mosi); - Self::new_inner( - inner, - tx_dma, - None, - Some(clk.map_into()), - Some(mosi.map_into()), - None, - None, - config, - ) - } - - pub fn new_rxonly( - inner: impl Peripheral

+ 'd, - rx_dma: Option>, - clk: impl Peripheral

+ 'd> + 'd, - miso: impl Peripheral

+ 'd> + 'd, - config: Config, - ) -> Self { - into_ref!(clk, miso); - Self::new_inner( - inner, - None, - rx_dma, - Some(clk.map_into()), - None, - Some(miso.map_into()), - None, - config, - ) - } - fn new_inner( inner: impl Peripheral

+ 'd, tx_dma: Option>, @@ -261,6 +201,66 @@ impl<'d, T: Instance, M: Mode> Spi<'d, T, M> { } } +impl<'d, T: Instance> Spi<'d, T, Blocking> { + pub fn new_blocking( + inner: impl Peripheral

+ 'd, + clk: impl Peripheral

+ 'd> + 'd, + mosi: impl Peripheral

+ 'd> + 'd, + miso: impl Peripheral

+ 'd> + 'd, + config: Config, + ) -> Self { + into_ref!(clk, mosi, miso); + Self::new_inner( + inner, + None, + None, + Some(clk.map_into()), + Some(mosi.map_into()), + Some(miso.map_into()), + None, + config, + ) + } + + pub fn new_blocking_txonly( + inner: impl Peripheral

+ 'd, + clk: impl Peripheral

+ 'd> + 'd, + mosi: impl Peripheral

+ 'd> + 'd, + config: Config, + ) -> Self { + into_ref!(clk, mosi); + Self::new_inner( + inner, + None, + None, + Some(clk.map_into()), + Some(mosi.map_into()), + None, + None, + config, + ) + } + + pub fn new_blocking_rxonly( + inner: impl Peripheral

+ 'd, + clk: impl Peripheral

+ 'd> + 'd, + miso: impl Peripheral

+ 'd> + 'd, + config: Config, + ) -> Self { + into_ref!(clk, miso); + Self::new_inner( + inner, + None, + None, + Some(clk.map_into()), + None, + Some(miso.map_into()), + None, + config, + ) + } +} + impl<'d, T: Instance> Spi<'d, T, Async> { pub fn new( inner: impl Peripheral

+ 'd, @@ -284,6 +284,46 @@ impl<'d, T: Instance> Spi<'d, T, Async> { ) } + pub fn new_txonly( + inner: impl Peripheral

+ 'd, + tx_dma: impl Peripheral

+ 'd, + clk: impl Peripheral

+ 'd> + 'd, + mosi: impl Peripheral

+ 'd> + 'd, + config: Config, + ) -> Self { + into_ref!(tx_dma, clk, mosi); + Self::new_inner( + inner, + Some(tx_dma.map_into()), + None, + Some(clk.map_into()), + Some(mosi.map_into()), + None, + None, + config, + ) + } + + pub fn new_rxonly( + inner: impl Peripheral

+ 'd, + rx_dma: impl Peripheral

+ 'd, + clk: impl Peripheral

+ 'd> + 'd, + miso: impl Peripheral

+ 'd> + 'd, + config: Config, + ) -> Self { + into_ref!(rx_dma, clk, miso); + Self::new_inner( + inner, + None, + Some(rx_dma.map_into()), + Some(clk.map_into()), + None, + Some(miso.map_into()), + None, + config, + ) + } + pub async fn write(&mut self, buffer: &[u8]) -> Result<(), Error> { let (from_ptr, len) = crate::dma::slice_ptr_parts(buffer); let ch = self.tx_dma.as_mut().unwrap(); @@ -293,7 +333,13 @@ impl<'d, T: Instance> Spi<'d, T, Async> { }); // If we don't assign future to a variable, the data register pointer // is held across an await and makes the future non-Send. - crate::dma::write(ch, from_ptr as *const u32, self.inner.regs().dr().ptr() as *mut _, len, T::TX_DREQ) + crate::dma::write( + ch, + from_ptr as *const u32, + self.inner.regs().dr().ptr() as *mut _, + len, + T::TX_DREQ, + ) }; transfer.await; Ok(()) @@ -308,7 +354,13 @@ impl<'d, T: Instance> Spi<'d, T, Async> { }); // If we don't assign future to a variable, the data register pointer // is held across an await and makes the future non-Send. - crate::dma::read(ch, self.inner.regs().dr().ptr() as *const _, to_ptr as *mut u32, len, T::RX_DREQ) + crate::dma::read( + ch, + self.inner.regs().dr().ptr() as *const _, + to_ptr as *mut u32, + len, + T::RX_DREQ, + ) }; transfer.await; Ok(()) diff --git a/embassy-rp/src/uart.rs b/embassy-rp/src/uart.rs index f8a10bd9..87d5fbd4 100644 --- a/embassy-rp/src/uart.rs +++ b/embassy-rp/src/uart.rs @@ -128,7 +128,13 @@ impl<'d, T: Instance> UartTx<'d, T, Async> { }); // If we don't assign future to a variable, the data register pointer // is held across an await and makes the future non-Send. - crate::dma::write(ch, from_ptr as *const u32, T::regs().uartdr().ptr() as *mut _, len, T::TX_DREQ) + crate::dma::write( + ch, + from_ptr as *const u32, + T::regs().uartdr().ptr() as *mut _, + len, + T::TX_DREQ, + ) }; transfer.await; Ok(()) @@ -182,7 +188,13 @@ impl<'d, T: Instance> UartRx<'d, T, Async> { }); // If we don't assign future to a variable, the data register pointer // is held across an await and makes the future non-Send. - crate::dma::read(ch, T::regs().uartdr().ptr() as *const _, to_ptr as *mut u32, len, T::RX_DREQ) + crate::dma::read( + ch, + T::regs().uartdr().ptr() as *const _, + to_ptr as *mut u32, + len, + T::RX_DREQ, + ) }; transfer.await; Ok(())