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cortex-m: remove owned interrupts.

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This commit is contained in:
Dario Nieuwenhuis
2023-06-01 02:22:46 +02:00
parent 2a435e53b7
commit 404aa29289
54 changed files with 239 additions and 439 deletions
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6
embassy-rp/src/adc.rs
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@ -8,7 +8,7 @@ use embassy_sync::waitqueue::AtomicWaker;
use embedded_hal_02::adc::{Channel, OneShot};
use crate::gpio::Pin;
use crate::interrupt::{self, InterruptExt, ADC_IRQ_FIFO};
use crate::interrupt::{self, ADC_IRQ_FIFO};
use crate::peripherals::ADC;
use crate::{pac, peripherals, Peripheral};
static WAKER: AtomicWaker = AtomicWaker::new();
@ -63,8 +63,8 @@ impl<'d> Adc<'d> {
// Setup IRQ
unsafe {
ADC_IRQ_FIFO::steal().unpend();
ADC_IRQ_FIFO::steal().enable();
ADC_IRQ_FIFO::unpend();
ADC_IRQ_FIFO::enable();
};
Self { phantom: PhantomData }

9
embassy-rp/src/dma.rs
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@ -4,7 +4,7 @@ use core::pin::Pin;
use core::sync::atomic::{compiler_fence, Ordering};
use core::task::{Context, Poll};
use embassy_cortex_m::interrupt::{Interrupt, InterruptExt};
use embassy_cortex_m::interrupt::Interrupt;
use embassy_hal_common::{impl_peripheral, into_ref, Peripheral, PeripheralRef};
use embassy_sync::waitqueue::AtomicWaker;
use pac::dma::vals::DataSize;
@ -29,13 +29,12 @@ unsafe fn DMA_IRQ_0() {
}
pub(crate) unsafe fn init() {
let irq = interrupt::DMA_IRQ_0::steal();
irq.disable();
irq.set_priority(interrupt::Priority::P3);
interrupt::DMA_IRQ_0::disable();
interrupt::DMA_IRQ_0::set_priority(interrupt::Priority::P3);
pac::DMA.inte0().write(|w| w.set_inte0(0xFFFF));
irq.enable();
interrupt::DMA_IRQ_0::enable();
}
pub unsafe fn read<'a, C: Channel, W: Word>(

9
embassy-rp/src/gpio.rs
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@ -3,7 +3,7 @@ use core::future::Future;
use core::pin::Pin as FuturePin;
use core::task::{Context, Poll};
use embassy_cortex_m::interrupt::{Interrupt, InterruptExt};
use embassy_cortex_m::interrupt::Interrupt;
use embassy_hal_common::{impl_peripheral, into_ref, PeripheralRef};
use embassy_sync::waitqueue::AtomicWaker;
@ -137,10 +137,9 @@ pub enum InterruptTrigger {
}
pub(crate) unsafe fn init() {
let irq = interrupt::IO_IRQ_BANK0::steal();
irq.disable();
irq.set_priority(interrupt::Priority::P3);
irq.enable();
interrupt::IO_IRQ_BANK0::disable();
interrupt::IO_IRQ_BANK0::set_priority(interrupt::Priority::P3);
interrupt::IO_IRQ_BANK0::enable();
}
#[interrupt]

14
embassy-rp/src/i2c.rs
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@ -2,7 +2,7 @@ use core::future;
use core::marker::PhantomData;
use core::task::Poll;
use embassy_cortex_m::interrupt::{self, Binding, Interrupt, InterruptExt};
use embassy_cortex_m::interrupt::{self, Binding, Interrupt};
use embassy_hal_common::{into_ref, PeripheralRef};
use embassy_sync::waitqueue::AtomicWaker;
use pac::i2c;
@ -82,14 +82,12 @@ impl<'d, T: Instance> I2c<'d, T, Async> {
let i2c = Self::new_inner(peri, scl.map_into(), sda.map_into(), config);
unsafe {
let i2c = T::regs();
let r = T::regs();
// mask everything initially
i2c.ic_intr_mask().write_value(i2c::regs::IcIntrMask(0));
T::Interrupt::steal().unpend();
T::Interrupt::steal().enable();
}
// mask everything initially
unsafe { r.ic_intr_mask().write_value(i2c::regs::IcIntrMask(0)) }
T::Interrupt::unpend();
unsafe { T::Interrupt::enable() };
i2c
}

2
embassy-rp/src/interrupt.rs
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@ -1,7 +1,7 @@
//! Interrupt definitions and macros to bind them.
pub use cortex_m::interrupt::{CriticalSection, Mutex};
use embassy_cortex_m::interrupt::_export::declare;
pub use embassy_cortex_m::interrupt::{Binding, Handler, Interrupt, InterruptExt, Priority};
pub use embassy_cortex_m::interrupt::{Binding, Handler, Interrupt, Priority};
use crate::pac::Interrupt as InterruptEnum;
declare!(TIMER_IRQ_0);

5
embassy-rp/src/multicore.rs
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@ -50,7 +50,7 @@
use core::mem::ManuallyDrop;
use core::sync::atomic::{compiler_fence, AtomicBool, Ordering};
use crate::interrupt::{Interrupt, InterruptExt};
use crate::interrupt::Interrupt;
use crate::peripherals::CORE1;
use crate::{gpio, interrupt, pac};
@ -156,8 +156,7 @@ where
IS_CORE1_INIT.store(true, Ordering::Release);
// Enable fifo interrupt on CORE1 for `pause` functionality.
let irq = unsafe { interrupt::SIO_IRQ_PROC1::steal() };
irq.enable();
unsafe { interrupt::SIO_IRQ_PROC1::enable() };
entry()
}

16
embassy-rp/src/pio.rs
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@ -5,7 +5,7 @@ use core::sync::atomic::{compiler_fence, Ordering};
use core::task::{Context, Poll};
use atomic_polyfill::{AtomicU32, AtomicU8};
use embassy_cortex_m::interrupt::{Interrupt, InterruptExt};
use embassy_cortex_m::interrupt::Interrupt;
use embassy_hal_common::{into_ref, Peripheral, PeripheralRef};
use embassy_sync::waitqueue::AtomicWaker;
use fixed::types::extra::U8;
@ -110,17 +110,15 @@ unsafe fn PIO1_IRQ_0() {
}
pub(crate) unsafe fn init() {
let irq = interrupt::PIO0_IRQ_0::steal();
irq.disable();
irq.set_priority(interrupt::Priority::P3);
interrupt::PIO0_IRQ_0::disable();
interrupt::PIO0_IRQ_0::set_priority(interrupt::Priority::P3);
pac::PIO0.irqs(0).inte().write(|m| m.0 = 0);
irq.enable();
interrupt::PIO0_IRQ_0::enable();
let irq = interrupt::PIO1_IRQ_0::steal();
irq.disable();
irq.set_priority(interrupt::Priority::P3);
interrupt::PIO1_IRQ_0::disable();
interrupt::PIO1_IRQ_0::set_priority(interrupt::Priority::P3);
pac::PIO1.irqs(0).inte().write(|m| m.0 = 0);
irq.enable();
interrupt::PIO1_IRQ_0::enable();
}
/// Future that waits for TX-FIFO to become writable

10
embassy-rp/src/timer.rs
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@ -6,7 +6,7 @@ use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
use embassy_sync::blocking_mutex::Mutex;
use embassy_time::driver::{AlarmHandle, Driver};
use crate::interrupt::{Interrupt, InterruptExt};
use crate::interrupt::Interrupt;
use crate::{interrupt, pac};
struct AlarmState {
@ -145,10 +145,10 @@ pub unsafe fn init() {
w.set_alarm(2, true);
w.set_alarm(3, true);
});
interrupt::TIMER_IRQ_0::steal().enable();
interrupt::TIMER_IRQ_1::steal().enable();
interrupt::TIMER_IRQ_2::steal().enable();
interrupt::TIMER_IRQ_3::steal().enable();
interrupt::TIMER_IRQ_0::enable();
interrupt::TIMER_IRQ_1::enable();
interrupt::TIMER_IRQ_2::enable();
interrupt::TIMER_IRQ_3::enable();
}
#[interrupt]

14
embassy-rp/src/uart/buffered.rs
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@ -3,7 +3,7 @@ use core::slice;
use core::task::Poll;
use atomic_polyfill::{AtomicU8, Ordering};
use embassy_cortex_m::interrupt::{self, Binding, Interrupt, InterruptExt};
use embassy_cortex_m::interrupt::{self, Binding, Interrupt};
use embassy_hal_common::atomic_ring_buffer::RingBuffer;
use embassy_sync::waitqueue::AtomicWaker;
use embassy_time::{Duration, Timer};
@ -80,8 +80,8 @@ pub(crate) fn init_buffers<'d, T: Instance + 'd>(
w.set_txim(true);
});
T::Interrupt::steal().unpend();
T::Interrupt::steal().enable();
T::Interrupt::unpend();
T::Interrupt::enable();
};
}
@ -362,7 +362,7 @@ impl<'d, T: Instance> BufferedUartTx<'d, T> {
// FIFO and the number of bytes drops below a threshold. When the
// FIFO was empty we have to manually pend the interrupt to shovel
// TX data from the buffer into the FIFO.
unsafe { T::Interrupt::steal() }.pend();
T::Interrupt::pend();
Poll::Ready(Ok(n))
})
}
@ -398,7 +398,7 @@ impl<'d, T: Instance> BufferedUartTx<'d, T> {
// FIFO and the number of bytes drops below a threshold. When the
// FIFO was empty we have to manually pend the interrupt to shovel
// TX data from the buffer into the FIFO.
unsafe { T::Interrupt::steal() }.pend();
T::Interrupt::pend();
return Ok(n);
}
}
@ -460,7 +460,7 @@ impl<'d, T: Instance> Drop for BufferedUartRx<'d, T> {
// TX is inactive if the the buffer is not available.
// We can now unregister the interrupt handler
if state.tx_buf.len() == 0 {
T::Interrupt::steal().disable();
T::Interrupt::disable();
}
}
}
@ -475,7 +475,7 @@ impl<'d, T: Instance> Drop for BufferedUartTx<'d, T> {
// RX is inactive if the the buffer is not available.
// We can now unregister the interrupt handler
if state.rx_buf.len() == 0 {
T::Interrupt::steal().disable();
T::Interrupt::disable();
}
}
}

14
embassy-rp/src/uart/mod.rs
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@ -3,7 +3,7 @@ use core::marker::PhantomData;
use core::task::Poll;
use atomic_polyfill::{AtomicU16, Ordering};
use embassy_cortex_m::interrupt::{self, Binding, Interrupt, InterruptExt};
use embassy_cortex_m::interrupt::{self, Binding, Interrupt};
use embassy_futures::select::{select, Either};
use embassy_hal_common::{into_ref, PeripheralRef};
use embassy_sync::waitqueue::AtomicWaker;
@ -245,12 +245,10 @@ impl<'d, T: Instance, M: Mode> UartRx<'d, T, M> {
fn new_inner(has_irq: bool, rx_dma: Option<PeripheralRef<'d, AnyChannel>>) -> Self {
debug_assert_eq!(has_irq, rx_dma.is_some());
if has_irq {
unsafe {
// disable all error interrupts initially
T::regs().uartimsc().write(|w| w.0 = 0);
T::Interrupt::steal().unpend();
T::Interrupt::steal().enable();
}
// disable all error interrupts initially
unsafe { T::regs().uartimsc().write(|w| w.0 = 0) }
T::Interrupt::unpend();
unsafe { T::Interrupt::enable() };
}
Self {
rx_dma,
@ -295,7 +293,7 @@ impl<'d, T: Instance, M: Mode> Drop for UartRx<'d, T, M> {
fn drop(&mut self) {
if let Some(_) = self.rx_dma {
unsafe {
T::Interrupt::steal().disable();
T::Interrupt::disable();
// clear dma flags. irq handlers use these to disambiguate among themselves.
T::regs().uartdmacr().write_clear(|reg| {
reg.set_rxdmae(true);

8
embassy-rp/src/usb.rs
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@ -11,7 +11,7 @@ use embassy_usb_driver::{
Direction, EndpointAddress, EndpointAllocError, EndpointError, EndpointInfo, EndpointType, Event, Unsupported,
};
use crate::interrupt::{Interrupt, InterruptExt};
use crate::interrupt::Interrupt;
use crate::{pac, peripherals, Peripheral, RegExt};
pub(crate) mod sealed {
@ -106,10 +106,8 @@ pub struct Driver<'d, T: Instance> {
impl<'d, T: Instance> Driver<'d, T> {
pub fn new(_usb: impl Peripheral<P = T> + 'd, _irq: impl Binding<T::Interrupt, InterruptHandler<T>>) -> Self {
unsafe {
T::Interrupt::steal().unpend();
T::Interrupt::steal().enable();
}
T::Interrupt::unpend();
unsafe { T::Interrupt::enable() };
let regs = T::regs();
unsafe {