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stm32: rename HSI16 -> HSI

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This commit is contained in:
Dario Nieuwenhuis
2023-10-22 22:39:55 +02:00
parent e70c531d3d
commit 412bcad2d1
22 changed files with 79 additions and 78 deletions
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20
embassy-stm32/src/rcc/l0l1.rs
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@ -18,20 +18,20 @@ pub enum ClockSrc {
MSI(MSIRange),
PLL(PLLSource, PLLMul, PLLDiv),
HSE(Hertz),
HSI16,
HSI,
}
/// PLL clock input source
#[derive(Clone, Copy)]
pub enum PLLSource {
HSI16,
HSI,
HSE(Hertz),
}
impl From<PLLSource> for Pllsrc {
fn from(val: PLLSource) -> Pllsrc {
match val {
PLLSource::HSI16 => Pllsrc::HSI,
PLLSource::HSI => Pllsrc::HSI,
PLLSource::HSE(_) => Pllsrc::HSE,
}
}
@ -83,10 +83,10 @@ pub(crate) unsafe fn init(config: Config) {
let freq = 32_768 * (1 << (range as u8 + 1));
(Hertz(freq), Sw::MSI)
}
ClockSrc::HSI16 => {
// Enable HSI16
RCC.cr().write(|w| w.set_hsi16on(true));
while !RCC.cr().read().hsi16rdy() {}
ClockSrc::HSI => {
// Enable HSI
RCC.cr().write(|w| w.set_hsion(true));
while !RCC.cr().read().hsirdy() {}
(HSI_FREQ, Sw::HSI)
}
@ -105,10 +105,10 @@ pub(crate) unsafe fn init(config: Config) {
while !RCC.cr().read().hserdy() {}
freq
}
PLLSource::HSI16 => {
PLLSource::HSI => {
// Enable HSI
RCC.cr().write(|w| w.set_hsi16on(true));
while !RCC.cr().read().hsi16rdy() {}
RCC.cr().write(|w| w.set_hsion(true));
while !RCC.cr().read().hsirdy() {}
HSI_FREQ
}
};