stm32/usart: merge v2 and v3 (they're identical)
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71c8d7aa7d
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4361cb15f1
@ -2,7 +2,6 @@
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#[cfg_attr(usart_v1, path = "v1.rs")]
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#[cfg_attr(usart_v1, path = "v1.rs")]
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#[cfg_attr(usart_v2, path = "v2.rs")]
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#[cfg_attr(usart_v2, path = "v2.rs")]
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#[cfg_attr(usart_v3, path = "v3.rs")]
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mod _version;
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mod _version;
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use crate::peripherals;
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use crate::peripherals;
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pub use _version::*;
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pub use _version::*;
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@ -3,29 +3,38 @@ use core::marker::PhantomData;
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use embassy::util::Unborrow;
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use embassy::util::Unborrow;
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use embassy_extras::unborrow;
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use embassy_extras::unborrow;
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use crate::pac::usart::vals;
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use crate::pac::usart::{regs, vals};
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use super::*;
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use super::*;
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use core::future::Future;
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use futures::TryFutureExt;
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pub struct Uart<'d, T: Instance> {
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use crate::dma_traits::NoDma;
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#[allow(dead_code)]
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pub struct Uart<'d, T: Instance, TxDma = NoDma, RxDma = NoDma> {
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inner: T,
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inner: T,
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phantom: PhantomData<&'d mut T>,
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phantom: PhantomData<&'d mut T>,
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tx_dma: TxDma,
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rx_dma: RxDma,
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}
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}
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impl<'d, T: Instance> Uart<'d, T> {
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impl<'d, T: Instance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
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pub fn new(
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pub fn new(
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inner: impl Unborrow<Target = T>,
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inner: impl Unborrow<Target = T>,
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rx: impl Unborrow<Target = impl RxPin<T>>,
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rx: impl Unborrow<Target = impl RxPin<T>>,
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tx: impl Unborrow<Target = impl TxPin<T>>,
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tx: impl Unborrow<Target = impl TxPin<T>>,
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tx_dma: impl Unborrow<Target = TxDma>,
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rx_dma: impl Unborrow<Target = RxDma>,
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config: Config,
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config: Config,
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) -> Self {
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) -> Self {
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unborrow!(inner, rx, tx);
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unborrow!(inner, rx, tx, tx_dma, rx_dma);
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T::enable();
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T::enable();
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let pclk_freq = T::frequency();
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let pclk_freq = T::frequency();
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// TODO: better calculation, including error checking and OVER8 if possible.
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// TODO: better calculation, including error checking and OVER8 if possible.
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let div = pclk_freq.0 / config.baudrate;
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let div = (pclk_freq.0 + (config.baudrate / 2)) / config.baudrate;
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let r = inner.regs();
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let r = inner.regs();
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@ -50,16 +59,23 @@ impl<'d, T: Instance> Uart<'d, T> {
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_ => vals::Ps::EVEN,
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_ => vals::Ps::EVEN,
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});
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});
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});
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});
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r.cr2().write(|_w| {});
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r.cr3().write(|_w| {});
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}
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}
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Self {
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Self {
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inner,
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inner,
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phantom: PhantomData,
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phantom: PhantomData,
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tx_dma,
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rx_dma,
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}
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}
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}
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}
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#[cfg(bdma)]
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async fn write_dma(&mut self, buffer: &[u8]) -> Result<(), Error>
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pub async fn write_dma(&mut self, ch: &mut impl TxDma<T>, buffer: &[u8]) -> Result<(), Error> {
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where
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TxDma: crate::usart::TxDma<T>,
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{
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let ch = &mut self.tx_dma;
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unsafe {
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unsafe {
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self.inner.regs().cr3().modify(|reg| {
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self.inner.regs().cr3().modify(|reg| {
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reg.set_dmat(true);
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reg.set_dmat(true);
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@ -83,6 +99,9 @@ impl<'d, T: Instance> Uart<'d, T> {
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} else if sr.fe() {
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} else if sr.fe() {
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r.rdr().read();
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r.rdr().read();
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return Err(Error::Framing);
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return Err(Error::Framing);
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} else if sr.nf() {
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r.rdr().read();
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return Err(Error::Noise);
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} else if sr.ore() {
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} else if sr.ore() {
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r.rdr().read();
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r.rdr().read();
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return Err(Error::Overrun);
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return Err(Error::Overrun);
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@ -97,14 +116,16 @@ impl<'d, T: Instance> Uart<'d, T> {
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}
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}
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}
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}
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impl<'d, T: Instance> embedded_hal::blocking::serial::Write<u8> for Uart<'d, T> {
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impl<'d, T: Instance, RxDma> embedded_hal::blocking::serial::Write<u8>
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for Uart<'d, T, NoDma, RxDma>
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{
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type Error = Error;
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type Error = Error;
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fn bwrite_all(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
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fn bwrite_all(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
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unsafe {
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unsafe {
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let r = self.inner.regs();
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let r = self.inner.regs();
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for &b in buffer {
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for &b in buffer {
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while !r.isr().read().txe() {}
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while !r.isr().read().txe() {}
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r.tdr().write(|w| w.set_dr(b as u16));
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r.tdr().write_value(regs::Dr(b as u32))
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}
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}
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}
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}
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Ok(())
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Ok(())
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@ -117,3 +138,15 @@ impl<'d, T: Instance> embedded_hal::blocking::serial::Write<u8> for Uart<'d, T>
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Ok(())
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Ok(())
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}
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}
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}
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}
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// rustfmt::skip because intellij removes the 'where' claus on the associated type.
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#[rustfmt::skip]
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impl<'d, T: Instance, TxDma, RxDma> embassy_traits::uart::Write for Uart<'d, T, TxDma, RxDma>
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where TxDma: crate::usart::TxDma<T>
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{
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type WriteFuture<'a> where Self: 'a = impl Future<Output = Result<(), embassy_traits::uart::Error>>;
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fn write<'a>(&'a mut self, buf: &'a [u8]) -> Self::WriteFuture<'a> {
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self.write_dma(buf).map_err(|_| embassy_traits::uart::Error::Other)
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}
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}
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@ -1,149 +0,0 @@
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use core::marker::PhantomData;
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use embassy::util::Unborrow;
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use embassy_extras::unborrow;
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use crate::pac::usart::{regs, vals};
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use super::*;
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use core::future::Future;
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use futures::TryFutureExt;
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use crate::dma_traits::NoDma;
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#[allow(dead_code)]
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pub struct Uart<'d, T: Instance, TxDma = NoDma, RxDma = NoDma> {
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inner: T,
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phantom: PhantomData<&'d mut T>,
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tx_dma: TxDma,
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rx_dma: RxDma,
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}
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impl<'d, T: Instance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
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pub fn new(
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inner: impl Unborrow<Target = T>,
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rx: impl Unborrow<Target = impl RxPin<T>>,
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tx: impl Unborrow<Target = impl TxPin<T>>,
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tx_dma: impl Unborrow<Target = TxDma>,
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rx_dma: impl Unborrow<Target = RxDma>,
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config: Config,
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) -> Self {
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unborrow!(inner, rx, tx, tx_dma, rx_dma);
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// Uncomment once we find all of the H7's UART clocks.
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T::enable();
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let pclk_freq = T::frequency();
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// TODO: better calculation, including error checking and OVER8 if possible.
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let div = (pclk_freq.0 + (config.baudrate / 2)) / config.baudrate;
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let r = inner.regs();
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unsafe {
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rx.set_as_af(rx.af_num());
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tx.set_as_af(tx.af_num());
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r.brr().write_value(regs::Brr(div));
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r.cr1().write(|w| {
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w.set_ue(true);
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w.set_te(true);
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w.set_re(true);
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w.set_m(0, vals::M0::BIT8);
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w.set_pce(config.parity != Parity::ParityNone);
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w.set_ps(match config.parity {
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Parity::ParityOdd => vals::Ps::ODD,
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Parity::ParityEven => vals::Ps::EVEN,
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_ => vals::Ps::EVEN,
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});
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});
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r.cr2().write(|_w| {});
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r.cr3().write(|_w| {});
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}
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Self {
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inner,
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phantom: PhantomData,
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tx_dma,
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rx_dma,
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}
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}
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async fn write_dma(&mut self, buffer: &[u8]) -> Result<(), Error>
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where
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TxDma: crate::usart::TxDma<T>,
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{
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let ch = &mut self.tx_dma;
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unsafe {
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self.inner.regs().cr3().modify(|reg| {
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reg.set_dmat(true);
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});
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}
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let r = self.inner.regs();
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let dst = r.tdr().ptr() as *mut u8;
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ch.transfer(buffer, dst).await;
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Ok(())
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}
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pub fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
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unsafe {
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let r = self.inner.regs();
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for b in buffer {
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loop {
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let sr = r.isr().read();
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if sr.pe() {
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r.rdr().read();
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return Err(Error::Parity);
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} else if sr.fe() {
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r.rdr().read();
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return Err(Error::Framing);
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} else if sr.ne() {
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r.rdr().read();
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return Err(Error::Noise);
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} else if sr.ore() {
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r.rdr().read();
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return Err(Error::Overrun);
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} else if sr.rxne() {
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break;
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}
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}
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*b = r.rdr().read().0 as u8;
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}
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}
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Ok(())
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}
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}
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impl<'d, T: Instance, RxDma> embedded_hal::blocking::serial::Write<u8>
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for Uart<'d, T, NoDma, RxDma>
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{
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type Error = Error;
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fn bwrite_all(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
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unsafe {
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let r = self.inner.regs();
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for &b in buffer {
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while !r.isr().read().txe() {}
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r.tdr().write_value(regs::Tdr(b as u32))
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}
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}
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Ok(())
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}
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fn bflush(&mut self) -> Result<(), Self::Error> {
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unsafe {
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let r = self.inner.regs();
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while !r.isr().read().tc() {}
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}
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Ok(())
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}
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}
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// rustfmt::skip because intellij removes the 'where' claus on the associated type.
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#[rustfmt::skip]
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impl<'d, T: Instance, TxDma, RxDma> embassy_traits::uart::Write for Uart<'d, T, TxDma, RxDma>
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where TxDma: crate::usart::TxDma<T>
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{
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type WriteFuture<'a> where Self: 'a = impl Future<Output = Result<(), embassy_traits::uart::Error>>;
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fn write<'a>(&'a mut self, buf: &'a [u8]) -> Self::WriteFuture<'a> {
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self.write_dma(buf).map_err(|_| embassy_traits::uart::Error::Other)
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}
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}
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@ -1 +1 @@
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Subproject commit 964bf38532aca5b8ecb274a38659b272db3d4d51
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Subproject commit b10a0dd9101038d9f93402565e9b9675f15c0871
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