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STM32 BDMA: Use interrupt flags instead of atomics

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This commit is contained in:
Timo Kröger 2021-07-22 14:52:16 +02:00 committed by Dario Nieuwenhuis
parent 5a4a5ce334
commit 43c4f24207
1 changed files with 22 additions and 30 deletions
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52
embassy-stm32/src/dma/bdma.rs
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@ -3,7 +3,6 @@
use core::future::Future; use core::future::Future;
use core::task::Poll; use core::task::Poll;
use atomic_polyfill::{AtomicU8, Ordering};
use embassy::interrupt::{Interrupt, InterruptExt}; use embassy::interrupt::{Interrupt, InterruptExt};
use embassy::util::{AtomicWaker, OnDrop}; use embassy::util::{AtomicWaker, OnDrop};
use futures::future::poll_fn; use futures::future::poll_fn;
@ -15,22 +14,16 @@ use crate::pac::bdma::vals;
use crate::rcc::sealed::RccPeripheral; use crate::rcc::sealed::RccPeripheral;
const CH_COUNT: usize = pac::peripheral_count!(bdma) * 8; const CH_COUNT: usize = pac::peripheral_count!(bdma) * 8;
const CH_STATUS_NONE: u8 = 0;
const CH_STATUS_COMPLETED: u8 = 1;
const CH_STATUS_ERROR: u8 = 2;
struct State { struct State {
ch_wakers: [AtomicWaker; CH_COUNT], ch_wakers: [AtomicWaker; CH_COUNT],
ch_status: [AtomicU8; CH_COUNT],
} }
impl State { impl State {
const fn new() -> Self { const fn new() -> Self {
const AW: AtomicWaker = AtomicWaker::new(); const AW: AtomicWaker = AtomicWaker::new();
const AU: AtomicU8 = AtomicU8::new(CH_STATUS_NONE);
Self { Self {
ch_wakers: [AW; CH_COUNT], ch_wakers: [AW; CH_COUNT],
ch_status: [AU; CH_COUNT],
} }
} }
} }
@ -57,21 +50,17 @@ pub(crate) unsafe fn do_transfer(
let ch = dma.ch(channel_number as _); let ch = dma.ch(channel_number as _);
// Reset status // Reset status
// Generate a DMB here to flush the store buffer (M7) before enabling the DMA dma.ifcr().write(|w| {
STATE.ch_status[state_number as usize].store(CH_STATUS_NONE, Ordering::Release); w.set_tcif(channel_number as _, true);
w.set_teif(channel_number as _, true);
});
let on_drop = OnDrop::new(move || unsafe { let on_drop = OnDrop::new(move || unsafe {
ch.cr().modify(|w| { // Disable the channel and interrupts with the default value.
w.set_tcie(false); ch.cr().write(|_| ());
w.set_teie(false);
w.set_en(false);
});
while ch.cr().read().en() {}
// Disabling the DMA mid transfer might cause some flags to be set, clear them all for the // Wait for the transfer to complete when it was ongoing.
// next transfer while ch.cr().read().en() {}
dma.ifcr()
.write(|w| w.set_gif(channel_number as usize, true));
}); });
#[cfg(dmamux)] #[cfg(dmamux)]
@ -103,15 +92,20 @@ pub(crate) unsafe fn do_transfer(
async move { async move {
let res = poll_fn(|cx| { let res = poll_fn(|cx| {
STATE.ch_wakers[state_number as usize].register(cx.waker()); STATE.ch_wakers[state_number as usize].register(cx.waker());
match STATE.ch_status[state_number as usize].load(Ordering::Acquire) {
CH_STATUS_NONE => Poll::Pending, let isr = dma.isr().read();
x => Poll::Ready(x),
// TODO handle error
assert!(!isr.teif(channel_number as _));
if isr.tcif(channel_number as _) {
Poll::Ready(())
} else {
Poll::Pending
} }
}) })
.await; .await;
// TODO handle error
assert!(res == CH_STATUS_COMPLETED);
drop(on_drop) drop(on_drop)
} }
} }
@ -136,12 +130,10 @@ unsafe fn on_irq() {
let dman = dma_num!($dma); let dman = dma_num!($dma);
for chn in 0..crate::pac::dma_channels_count!($dma) { for chn in 0..crate::pac::dma_channels_count!($dma) {
let n = dman * 8 + chn; let cr = pac::$dma.ch(chn).cr();
if isr.teif(chn) { if isr.tcif(chn) && cr.read().tcie() {
STATE.ch_status[n].store(CH_STATUS_ERROR, Ordering::Relaxed); cr.write(|_| ()); // Disable channel interrupts with the default value.
STATE.ch_wakers[n].wake(); let n = dma_num!($dma) * 8 + chn;
} else if isr.tcif(chn) {
STATE.ch_status[n].store(CH_STATUS_COMPLETED, Ordering::Relaxed);
STATE.ch_wakers[n].wake(); STATE.ch_wakers[n].wake();
} }
} }