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Add flush_rx_fifo function

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This commit is contained in:
Grant Miller 2022-03-14 15:10:56 -05:00
parent 683c11f399
commit 444b37fcdf
4 changed files with 37 additions and 20 deletions
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13
embassy-stm32/src/spi/mod.rs
View File

@ -614,6 +614,19 @@ fn spin_until_idle(regs: Regs) {
} }
} }
fn flush_rx_fifo(regs: Regs) {
unsafe {
#[cfg(not(spi_v3))]
while regs.sr().read().rxne() {
let _ = regs.dr().read();
}
#[cfg(spi_v3)]
while regs.sr().read().rxp() {
let _ = regs.rxdr().read();
}
}
}
fn finish_dma(regs: Regs) { fn finish_dma(regs: Regs) {
spin_until_idle(regs); spin_until_idle(regs);

8
embassy-stm32/src/spi/v1.rs
View File

@ -17,6 +17,10 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
}); });
} }
// TODO: This is unnecessary in some versions because
// clearing SPE automatically clears the fifos
flush_rx_fifo(T::regs());
let tx_request = self.txdma.request(); let tx_request = self.txdma.request();
let tx_dst = T::regs().tx_ptr(); let tx_dst = T::regs().tx_ptr();
unsafe { self.txdma.start_write(tx_request, write, tx_dst) } unsafe { self.txdma.start_write(tx_request, write, tx_dst) }
@ -110,6 +114,10 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
}); });
} }
// TODO: This is unnecessary in some versions because
// clearing SPE automatically clears the fifos
flush_rx_fifo(T::regs());
let rx_request = self.rxdma.request(); let rx_request = self.rxdma.request();
let rx_src = T::regs().rx_ptr(); let rx_src = T::regs().rx_ptr();
unsafe { self.rxdma.start_read(rx_request, rx_src, read) }; unsafe { self.rxdma.start_read(rx_request, rx_src, read) };

18
embassy-stm32/src/spi/v2.rs
View File

@ -15,12 +15,11 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
T::regs().cr1().modify(|w| { T::regs().cr1().modify(|w| {
w.set_spe(false); w.set_spe(false);
}); });
}
// Flush the read buffer to avoid errornous data from being read // TODO: This is unnecessary in some versions because
while T::regs().sr().read().rxne() { // clearing SPE automatically clears the fifos
let _ = T::regs().dr().read(); flush_rx_fifo(T::regs());
}
}
let tx_request = self.txdma.request(); let tx_request = self.txdma.request();
let tx_dst = T::regs().tx_ptr(); let tx_dst = T::regs().tx_ptr();
@ -113,12 +112,11 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
T::regs().cr2().modify(|reg| { T::regs().cr2().modify(|reg| {
reg.set_rxdmaen(true); reg.set_rxdmaen(true);
}); });
}
// Flush the read buffer to avoid errornous data from being read // TODO: This is unnecessary in some versions because
while T::regs().sr().read().rxne() { // clearing SPE automatically clears the fifos
let _ = T::regs().dr().read(); flush_rx_fifo(T::regs());
}
}
let rx_request = self.rxdma.request(); let rx_request = self.rxdma.request();
let rx_src = T::regs().rx_ptr(); let rx_src = T::regs().rx_ptr();

18
embassy-stm32/src/spi/v3.rs
View File

@ -15,12 +15,11 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
T::regs().cr1().modify(|w| { T::regs().cr1().modify(|w| {
w.set_spe(false); w.set_spe(false);
}); });
}
// Flush the read buffer to avoid errornous data from being read // TODO: This is unnecessary in some versions because
while T::regs().sr().read().rxp() { // clearing SPE automatically clears the fifos
let _ = T::regs().rxdr().read(); flush_rx_fifo(T::regs());
}
}
let tx_request = self.txdma.request(); let tx_request = self.txdma.request();
let tx_dst = T::regs().tx_ptr(); let tx_dst = T::regs().tx_ptr();
@ -119,12 +118,11 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
T::regs().cfg1().modify(|reg| { T::regs().cfg1().modify(|reg| {
reg.set_rxdmaen(true); reg.set_rxdmaen(true);
}); });
}
// Flush the read buffer to avoid errornous data from being read // TODO: This is unnecessary in some versions because
while T::regs().sr().read().rxp() { // clearing SPE automatically clears the fifos
let _ = T::regs().rxdr().read(); flush_rx_fifo(T::regs());
}
}
let rx_request = self.rxdma.request(); let rx_request = self.rxdma.request();
let rx_src = T::regs().rx_ptr(); let rx_src = T::regs().rx_ptr();