From 459049d60436e177a628df0104959b7789e710af Mon Sep 17 00:00:00 2001 From: Ulf Lilleengen Date: Tue, 8 Jun 2021 10:57:52 +0200 Subject: [PATCH] Workaround for L4 --- stm32-metapac/build.rs | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/stm32-metapac/build.rs b/stm32-metapac/build.rs index 46660d9b..72750267 100644 --- a/stm32-metapac/build.rs +++ b/stm32-metapac/build.rs @@ -219,17 +219,22 @@ fn main() { } "spi" => { if let Some(clock) = &p.clock { - // Workaround for APB1 register being split on some chip families - let reg = if chip.family == "STM32H7" && clock == "APB1" { - format!("{}l", clock.to_ascii_lowercase()) + // Workaround for APB1 register being split on some chip families. Assume + // first register until we can find a way to hint which register is used + let reg = clock.to_ascii_lowercase(); + let (enable_reg, reset_reg) = if chip.family == "STM32H7" && clock == "APB1" + { + (format!("{}lenr", reg), format!("{}lrstr", reg)) + } else if chip.family == "STM32L4" && clock == "APB1" { + (format!("{}enr1", reg), format!("{}rstr1", reg)) } else { - clock.to_ascii_lowercase() + (format!("{}enr", reg), format!("{}rstr", reg)) }; let field = name.to_ascii_lowercase(); peripheral_rcc_table.push(vec![ name.clone(), - format!("{}enr", reg), - format!("{}rstr", reg), + enable_reg, + reset_reg, format!("set_{}en", field), format!("set_{}rst", field), ]);