From 2aaf4bf96b960d6379b4c089145031d18c065aa3 Mon Sep 17 00:00:00 2001
From: JuliDi <20155974+JuliDi@users.noreply.github.com>
Date: Sun, 15 Oct 2023 19:14:34 +0200
Subject: [PATCH 1/2] fix typo in build.rs that caused fmc ClkPin to not be
 implemented

---
 embassy-stm32/build.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs
index 8e680fb6..710e1185 100644
--- a/embassy-stm32/build.rs
+++ b/embassy-stm32/build.rs
@@ -797,7 +797,7 @@ fn main() {
         (("fmc", "NCE"), quote!(crate::fmc::NCEPin)),
         (("fmc", "NOE"), quote!(crate::fmc::NOEPin)),
         (("fmc", "NWE"), quote!(crate::fmc::NWEPin)),
-        (("fmc", "Clk"), quote!(crate::fmc::ClkPin)),
+        (("fmc", "CLK"), quote!(crate::fmc::ClkPin)),
         (("fmc", "BA0"), quote!(crate::fmc::BA0Pin)),
         (("fmc", "BA1"), quote!(crate::fmc::BA1Pin)),
         (("timer", "CH1"), quote!(crate::timer::Channel1Pin)),

From b1e5b6ffe1587362d4a58f5da831338dfa41a1bc Mon Sep 17 00:00:00 2001
From: JuliDi <20155974+JuliDi@users.noreply.github.com>
Date: Sat, 28 Oct 2023 13:50:02 +0200
Subject: [PATCH 2/2] Add raw fmc access implementation

---
 embassy-stm32/src/fmc.rs | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/embassy-stm32/src/fmc.rs b/embassy-stm32/src/fmc.rs
index d6e25996..dd0d2721 100644
--- a/embassy-stm32/src/fmc.rs
+++ b/embassy-stm32/src/fmc.rs
@@ -12,6 +12,37 @@ pub struct Fmc<'d, T: Instance> {
 
 unsafe impl<'d, T> Send for Fmc<'d, T> where T: Instance {}
 
+impl<'d, T> Fmc<'d, T>
+where
+    T: Instance,
+{
+    /// Create a raw FMC instance.
+    ///
+    /// **Note:** This is currently used to provide access to some basic FMC functions
+    /// for manual configuration for memory types that stm32-fmc does not support.
+    pub fn new_raw(_instance: impl Peripheral<P = T> + 'd) -> Self {
+        Self { peri: PhantomData }
+    }
+
+    /// Enable the FMC peripheral and reset it.
+    pub fn enable(&mut self) {
+        T::enable_and_reset();
+    }
+
+    /// Enable the memory controller on applicable chips.
+    pub fn memory_controller_enable(&mut self) {
+        // fmc v1 and v2 does not have the fmcen bit
+        // fsmc v1, v2 and v3 does not have the fmcen bit
+        // This is a "not" because it is expected that all future versions have this bit
+        #[cfg(not(any(fmc_v1x3, fmc_v2x1, fsmc_v1x0, fsmc_v1x3, fsmc_v2x3, fsmc_v3x1)))]
+        T::REGS.bcr1().modify(|r| r.set_fmcen(true));
+    }
+
+    pub fn source_clock_hz(&self) -> u32 {
+        <T as crate::rcc::sealed::RccPeripheral>::frequency().0
+    }
+}
+
 unsafe impl<'d, T> stm32_fmc::FmcPeripheral for Fmc<'d, T>
 where
     T: Instance,