From 473a83a937ed03c844da8dd72bc6a1dc089367e1 Mon Sep 17 00:00:00 2001 From: Bob McWhirter Date: Thu, 22 Jul 2021 09:28:42 -0400 Subject: [PATCH] Adjust how we deal with read/write being different length. Including some docs about it. Removing the Rx-enablement for write-only operations. --- embassy-stm32/src/spi/v1.rs | 7 +++---- embassy-stm32/src/spi/v2.rs | 7 +++---- embassy-stm32/src/spi/v3.rs | 3 ++- embassy-traits/src/spi.rs | 3 +++ 4 files changed, 11 insertions(+), 9 deletions(-) diff --git a/embassy-stm32/src/spi/v1.rs b/embassy-stm32/src/spi/v1.rs index 72bde898..b4ebe5a6 100644 --- a/embassy-stm32/src/spi/v1.rs +++ b/embassy-stm32/src/spi/v1.rs @@ -151,9 +151,6 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> { T::regs().cr1().modify(|w| { w.set_spe(false); }); - T::regs().cr2().modify(|reg| { - reg.set_rxdmaen(true); - }); } self.set_word_size(WordSize::EightBit); @@ -233,6 +230,8 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> { Tx: TxDmaChannel, Rx: RxDmaChannel, { + assert!(read.len() >= write.len()); + unsafe { T::regs().cr1().modify(|w| { w.set_spe(false); @@ -245,7 +244,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> { let rx_request = self.rxdma.request(); let rx_src = T::regs().dr().ptr() as *mut u8; - let rx_f = self.rxdma.read(rx_request, rx_src, read); + let rx_f = self.rxdma.read(rx_request, rx_src, read[0..write.len()]); let tx_request = self.txdma.request(); let tx_dst = T::regs().dr().ptr() as *mut u8; diff --git a/embassy-stm32/src/spi/v2.rs b/embassy-stm32/src/spi/v2.rs index 400fd89a..9ca3e3c1 100644 --- a/embassy-stm32/src/spi/v2.rs +++ b/embassy-stm32/src/spi/v2.rs @@ -163,9 +163,6 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> { T::regs().cr1().modify(|w| { w.set_spe(false); }); - T::regs().cr2().modify(|reg| { - reg.set_rxdmaen(true); - }); } Self::set_word_size(WordSize::EightBit); @@ -245,6 +242,8 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> { Tx: TxDmaChannel, Rx: RxDmaChannel, { + assert!(read.len() >= write.len()); + unsafe { T::regs().cr1().modify(|w| { w.set_spe(false); @@ -257,7 +256,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> { let rx_request = self.rxdma.request(); let rx_src = T::regs().dr().ptr() as *mut u8; - let rx_f = self.rxdma.read(rx_request, rx_src, read); + let rx_f = self.rxdma.read(rx_request, rx_src, read[0..write.len()]); let tx_request = self.txdma.request(); let tx_dst = T::regs().dr().ptr() as *mut u8; diff --git a/embassy-stm32/src/spi/v3.rs b/embassy-stm32/src/spi/v3.rs index 2d6f4a28..f433d7f9 100644 --- a/embassy-stm32/src/spi/v3.rs +++ b/embassy-stm32/src/spi/v3.rs @@ -207,7 +207,6 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> { f.await; unsafe { T::regs().cfg1().modify(|reg| { - reg.set_rxdmaen(false); reg.set_txdmaen(false); }); T::regs().cr1().modify(|w| { @@ -278,6 +277,8 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> { Tx: TxDmaChannel, Rx: RxDmaChannel, { + assert!(read.len() >= write.len()); + Self::set_word_size(WordSize::EightBit); unsafe { T::regs().cr1().modify(|w| { diff --git a/embassy-traits/src/spi.rs b/embassy-traits/src/spi.rs index 9d044dfd..04322ddd 100644 --- a/embassy-traits/src/spi.rs +++ b/embassy-traits/src/spi.rs @@ -29,6 +29,9 @@ pub trait FullDuplex: Spi + Write + Read { where Self: 'a; + /// The `read` array must be at least as long as the `write` array, + /// but is guaranteed to only be filled with bytes equal to the + /// length of the `write` array. fn read_write<'a>( &'a mut self, read: &'a mut [Word],