diff --git a/embassy-net-adin1110/src/lib.rs b/embassy-net-adin1110/src/lib.rs index e0af7bde..53f36128 100644 --- a/embassy-net-adin1110/src/lib.rs +++ b/embassy-net-adin1110/src/lib.rs @@ -32,6 +32,7 @@ pub use regs::{Config0, Config2, SpiRegisters as sr, Status0, Status1}; use crate::fmt::Bytes; use crate::regs::{LedCntrl, LedFunc, LedPol, LedPolarity, SpiHeader}; +/// ADIN1110 intern PHY ID pub const PHYID: u32 = 0x0283_BC91; /// Error values ADIN1110 @@ -53,7 +54,9 @@ pub enum AdinError { MDIO_ACC_TIMEOUT, } +/// Type alias `Result` type with `AdinError` as error type. pub type AEResult = core::result::Result>; + /// Internet PHY address pub const MDIO_PHY_ADDR: u8 = 0x01; @@ -104,6 +107,7 @@ impl State { } } +/// ADIN1110 embassy-net driver #[derive(Debug)] pub struct ADIN1110 { /// SPI bus @@ -116,6 +120,7 @@ pub struct ADIN1110 { } impl ADIN1110 { + /// Create a new ADIN1110 instance. pub fn new(spi: SPI, spi_crc: bool, append_fcs_on_tx: bool) -> Self { Self { spi, @@ -124,6 +129,7 @@ impl ADIN1110 { } } + /// Read a SPI register pub async fn read_reg(&mut self, reg: sr) -> AEResult { let mut tx_buf = Vec::::new(); @@ -162,6 +168,7 @@ impl ADIN1110 { Ok(value) } + /// Write a SPI register pub async fn write_reg(&mut self, reg: sr, value: u32) -> AEResult<(), SPI::Error> { let mut tx_buf = Vec::::new(); @@ -427,9 +434,9 @@ impl mdio::MdioBus for ADIN1110 { } } -/// Background runner for the ADIN110. +/// Background runner for the ADIN1110. /// -/// You must call `.run()` in a background task for the ADIN1100 to operate. +/// You must call `.run()` in a background task for the ADIN1110 to operate. pub struct Runner<'d, SPI, INT, RST> { mac: ADIN1110, ch: ch::Runner<'d, MTU>, diff --git a/embassy-net-adin1110/src/mdio.rs b/embassy-net-adin1110/src/mdio.rs index 68477006..1ae5f004 100644 --- a/embassy-net-adin1110/src/mdio.rs +++ b/embassy-net-adin1110/src/mdio.rs @@ -32,11 +32,12 @@ enum Reg13Op { PostReadIncAddr = 0b10 << 14, Read = 0b11 << 14, } + /// `MdioBus` trait /// Driver needs to implement the Clause 22 /// Optional Clause 45 is the device supports this. /// -/// Claus 45 methodes are bases on +/// Clause 45 methodes are bases on pub trait MdioBus { type Error; @@ -87,89 +88,89 @@ pub trait MdioBus { } } -// #[cfg(test)] -// mod tests { -// use core::convert::Infallible; +#[cfg(test)] +mod tests { + use core::convert::Infallible; -// use super::{MdioBus, PhyAddr, RegC22, RegVal}; + use super::{MdioBus, PhyAddr, RegC22, RegVal}; -// #[derive(Debug, PartialEq, Eq)] -// enum A { -// Read(PhyAddr, RegC22), -// Write(PhyAddr, RegC22, RegVal), -// } + #[derive(Debug, PartialEq, Eq)] + enum A { + Read(PhyAddr, RegC22), + Write(PhyAddr, RegC22, RegVal), + } -// struct MockMdioBus(Vec); + struct MockMdioBus(Vec); -// impl MockMdioBus { -// pub fn clear(&mut self) { -// self.0.clear(); -// } -// } + impl MockMdioBus { + pub fn clear(&mut self) { + self.0.clear(); + } + } -// impl MdioBus for MockMdioBus { -// type Error = Infallible; + impl MdioBus for MockMdioBus { + type Error = Infallible; -// fn write_cl22( -// &mut self, -// phy_id: super::PhyAddr, -// reg: super::RegC22, -// reg_val: super::RegVal, -// ) -> Result<(), Self::Error> { -// self.0.push(A::Write(phy_id, reg, reg_val)); -// Ok(()) -// } + async fn write_cl22( + &mut self, + phy_id: super::PhyAddr, + reg: super::RegC22, + reg_val: super::RegVal, + ) -> Result<(), Self::Error> { + self.0.push(A::Write(phy_id, reg, reg_val)); + Ok(()) + } -// fn read_cl22( -// &mut self, -// phy_id: super::PhyAddr, -// reg: super::RegC22, -// ) -> Result { -// self.0.push(A::Read(phy_id, reg)); -// Ok(0) -// } -// } + async fn read_cl22( + &mut self, + phy_id: super::PhyAddr, + reg: super::RegC22, + ) -> Result { + self.0.push(A::Read(phy_id, reg)); + Ok(0) + } + } -// #[test] -// fn read_test() { -// let mut mdiobus = MockMdioBus(Vec::with_capacity(20)); + #[futures_test::test] + async fn read_test() { + let mut mdiobus = MockMdioBus(Vec::with_capacity(20)); -// mdiobus.clear(); -// mdiobus.read_cl22(0x01, 0x00).unwrap(); -// assert_eq!(mdiobus.0, vec![A::Read(0x01, 0x00)]); + mdiobus.clear(); + mdiobus.read_cl22(0x01, 0x00).await.unwrap(); + assert_eq!(mdiobus.0, vec![A::Read(0x01, 0x00)]); -// mdiobus.clear(); -// mdiobus.read_cl45(0x01, (0xBB, 0x1234)).unwrap(); -// assert_eq!( -// mdiobus.0, -// vec![ -// #[allow(clippy::identity_op)] -// A::Write(0x01, 13, (0b00 << 14) | 27), -// A::Write(0x01, 14, 0x1234), -// A::Write(0x01, 13, (0b11 << 14) | 27), -// A::Read(0x01, 14) -// ] -// ); -// } + mdiobus.clear(); + mdiobus.read_cl45(0x01, (0xBB, 0x1234)).await.unwrap(); + assert_eq!( + mdiobus.0, + vec![ + #[allow(clippy::identity_op)] + A::Write(0x01, 13, (0b00 << 14) | 27), + A::Write(0x01, 14, 0x1234), + A::Write(0x01, 13, (0b11 << 14) | 27), + A::Read(0x01, 14) + ] + ); + } -// #[test] -// fn write_test() { -// let mut mdiobus = MockMdioBus(Vec::with_capacity(20)); + #[futures_test::test] + async fn write_test() { + let mut mdiobus = MockMdioBus(Vec::with_capacity(20)); -// mdiobus.clear(); -// mdiobus.write_cl22(0x01, 0x00, 0xABCD).unwrap(); -// assert_eq!(mdiobus.0, vec![A::Write(0x01, 0x00, 0xABCD)]); + mdiobus.clear(); + mdiobus.write_cl22(0x01, 0x00, 0xABCD).await.unwrap(); + assert_eq!(mdiobus.0, vec![A::Write(0x01, 0x00, 0xABCD)]); -// mdiobus.clear(); -// mdiobus.write_cl45(0x01, (0xBB, 0x1234), 0xABCD).unwrap(); -// assert_eq!( -// mdiobus.0, -// vec![ -// A::Write(0x01, 13, 27), -// A::Write(0x01, 14, 0x1234), -// A::Write(0x01, 13, (0b01 << 14) | 27), -// A::Write(0x01, 14, 0xABCD) -// ] -// ); -// } -// } + mdiobus.clear(); + mdiobus.write_cl45(0x01, (0xBB, 0x1234), 0xABCD).await.unwrap(); + assert_eq!( + mdiobus.0, + vec![ + A::Write(0x01, 13, 27), + A::Write(0x01, 14, 0x1234), + A::Write(0x01, 13, (0b01 << 14) | 27), + A::Write(0x01, 14, 0xABCD) + ] + ); + } +} diff --git a/embassy-net-adin1110/src/phy.rs b/embassy-net-adin1110/src/phy.rs index 176ad019..d54d843d 100644 --- a/embassy-net-adin1110/src/phy.rs +++ b/embassy-net-adin1110/src/phy.rs @@ -111,6 +111,7 @@ pub mod RegsC45 { } } +/// 10-BASE-T1x PHY functions. pub struct Phy10BaseT1x(u8); impl Default for Phy10BaseT1x {