Add stm32 flash + bootloader support

* Add flash drivers for L0, L1, L4, WB and WL. Not tested for WB, but
should be similar to WL.
* Add embassy-boot-stm32 for bootloading on STM32.
* Add flash examples and bootloader examples
* Update stm32-data

embassy-stm32/Cargo.toml

@@ -42,6 +42,9 @@ embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = ["un
 embedded-hal-1 = { package = "embedded-hal", version = "1.0.0-alpha.8", optional = true}
 embedded-hal-async = { version = "0.1.0-alpha.0", optional = true}
 
+embedded-storage = "0.3.0"
+embedded-storage-async = { version = "0.3.0", optional = true }
+
 defmt = { version = "0.3", optional = true }
 log = { version = "0.4.14", optional = true }
 cortex-m-rt = ">=0.6.15,<0.8"
@@ -87,7 +90,7 @@ time-driver-tim12 = ["_time-driver"]
 time-driver-tim15 = ["_time-driver"]
 
 # Enable nightly-only features
-nightly = ["embassy/nightly", "embedded-hal-1", "embedded-hal-async"]
+nightly = ["embassy/nightly", "embedded-hal-1", "embedded-hal-async", "embedded-storage-async"]
 
 # Reexport stm32-metapac at `embassy_stm32::pac`.
 # This is unstable because semver-minor (non-breaking) releases of embassy-stm32 may major-bump (breaking) the stm32-metapac version.

embassy-stm32/src/flash/mod.rs

@@ -0,0 +1,401 @@
+use crate::pac;
+use crate::peripherals::FLASH;
+use core::convert::TryInto;
+use core::marker::PhantomData;
+use core::ptr::write_volatile;
+use embassy::util::Unborrow;
+use embassy_hal_common::unborrow;
+
+use embedded_storage::nor_flash::{
+    ErrorType, NorFlash, NorFlashError, NorFlashErrorKind, ReadNorFlash,
+};
+
+const FLASH_BASE: usize = 0x8000000;
+
+#[cfg(flash_l4)]
+mod config {
+    use super::*;
+    pub(crate) const FLASH_SIZE: usize = 0x100000;
+    pub(crate) const FLASH_START: usize = FLASH_BASE;
+    pub(crate) const FLASH_END: usize = FLASH_START + FLASH_SIZE;
+    pub(crate) const PAGE_SIZE: usize = 2048;
+    pub(crate) const WORD_SIZE: usize = 8;
+}
+
+#[cfg(flash_wb)]
+mod config {
+    use super::*;
+    pub(crate) const FLASH_SIZE: usize = 0x100000;
+    pub(crate) const FLASH_START: usize = FLASH_BASE;
+    pub(crate) const FLASH_END: usize = FLASH_START + FLASH_SIZE;
+    pub(crate) const PAGE_SIZE: usize = 4096;
+    pub(crate) const WORD_SIZE: usize = 8;
+}
+
+#[cfg(flash_wl)]
+mod config {
+    use super::*;
+    pub(crate) const FLASH_SIZE: usize = 0x40000;
+    pub(crate) const FLASH_START: usize = FLASH_BASE;
+    pub(crate) const FLASH_END: usize = FLASH_START + FLASH_SIZE;
+    pub(crate) const PAGE_SIZE: usize = 2048;
+    pub(crate) const WORD_SIZE: usize = 8;
+}
+
+#[cfg(flash_l0)]
+mod config {
+    use super::*;
+    pub(crate) const FLASH_SIZE: usize = 0x30000;
+    pub(crate) const FLASH_START: usize = FLASH_BASE;
+    pub(crate) const FLASH_END: usize = FLASH_START + FLASH_SIZE;
+    pub(crate) const PAGE_SIZE: usize = 128;
+    pub(crate) const WORD_SIZE: usize = 4;
+}
+
+#[cfg(flash_l1)]
+mod config {
+    use super::*;
+    pub(crate) const FLASH_SIZE: usize = 0x80000;
+    pub(crate) const FLASH_START: usize = FLASH_BASE;
+    pub(crate) const FLASH_END: usize = FLASH_START + FLASH_SIZE;
+    pub(crate) const PAGE_SIZE: usize = 256;
+    pub(crate) const WORD_SIZE: usize = 4;
+}
+
+use config::*;
+
+pub struct Flash<'d> {
+    _inner: FLASH,
+    _phantom: PhantomData<&'d mut FLASH>,
+}
+
+impl<'d> Flash<'d> {
+    pub fn new(p: impl Unborrow<Target = FLASH>) -> Self {
+        unborrow!(p);
+        Self {
+            _inner: p,
+            _phantom: PhantomData,
+        }
+    }
+
+    pub fn unlock(p: impl Unborrow<Target = FLASH>) -> Self {
+        let flash = Self::new(p);
+        #[cfg(any(flash_wl, flash_wb, flash_l4))]
+        unsafe {
+            pac::FLASH.keyr().write(|w| w.set_keyr(0x4567_0123));
+            pac::FLASH.keyr().write(|w| w.set_keyr(0xCDEF_89AB));
+        }
+
+        #[cfg(any(flash_l0))]
+        unsafe {
+            pac::FLASH.pekeyr().write(|w| w.set_pekeyr(0x89ABCDEF));
+            pac::FLASH.pekeyr().write(|w| w.set_pekeyr(0x02030405));
+
+            pac::FLASH.prgkeyr().write(|w| w.set_prgkeyr(0x8C9DAEBF));
+            pac::FLASH.prgkeyr().write(|w| w.set_prgkeyr(0x13141516));
+        }
+        flash
+    }
+
+    pub fn lock(&mut self) {
+        #[cfg(any(flash_wl, flash_wb, flash_l4))]
+        unsafe {
+            pac::FLASH.cr().modify(|w| w.set_lock(true));
+        }
+
+        #[cfg(any(flash_l0))]
+        unsafe {
+            pac::FLASH.pecr().modify(|w| {
+                w.set_optlock(true);
+                w.set_prglock(true);
+                w.set_pelock(true);
+            });
+        }
+    }
+
+    pub fn blocking_read(&mut self, offset: u32, bytes: &mut [u8]) -> Result<(), Error> {
+        if offset as usize >= FLASH_END || offset as usize + bytes.len() > FLASH_END {
+            return Err(Error::Size);
+        }
+
+        let flash_data = unsafe { core::slice::from_raw_parts(offset as *const u8, bytes.len()) };
+        bytes.copy_from_slice(flash_data);
+        Ok(())
+    }
+
+    pub fn blocking_write(&mut self, offset: u32, buf: &[u8]) -> Result<(), Error> {
+        if offset as usize + buf.len() > FLASH_END {
+            return Err(Error::Size);
+        }
+        if offset as usize % WORD_SIZE != 0 || buf.len() as usize % WORD_SIZE != 0 {
+            return Err(Error::Unaligned);
+        }
+
+        self.clear_all_err();
+
+        #[cfg(any(flash_wl, flash_wb, flash_l4))]
+        unsafe {
+            pac::FLASH.cr().write(|w| w.set_pg(true));
+        }
+
+        let mut ret: Result<(), Error> = Ok(());
+        let mut offset = offset;
+        for chunk in buf.chunks(WORD_SIZE) {
+            for val in chunk.chunks(4) {
+                unsafe {
+                    write_volatile(
+                        offset as *mut u32,
+                        u32::from_le_bytes(val[0..4].try_into().unwrap()),
+                    );
+                }
+                offset += val.len() as u32;
+            }
+
+            ret = self.blocking_wait_ready();
+            if ret.is_err() {
+                break;
+            }
+        }
+
+        #[cfg(any(flash_wl, flash_wb, flash_l4))]
+        unsafe {
+            pac::FLASH.cr().write(|w| w.set_pg(false));
+        }
+
+        ret
+    }
+
+    pub fn blocking_erase(&mut self, from: u32, to: u32) -> Result<(), Error> {
+        if to < from || to as usize > FLASH_END {
+            return Err(Error::Size);
+        }
+        if from as usize % PAGE_SIZE != 0 || to as usize % PAGE_SIZE != 0 {
+            return Err(Error::Unaligned);
+        }
+
+        self.clear_all_err();
+
+        for page in (from..to).step_by(PAGE_SIZE) {
+            #[cfg(any(flash_l0, flash_l1))]
+            unsafe {
+                pac::FLASH.pecr().modify(|w| {
+                    w.set_erase(true);
+                    w.set_prog(true);
+                });
+
+                write_volatile(page as *mut u32, 0xFFFFFFFF);
+            }
+
+            #[cfg(any(flash_wl, flash_wb, flash_l4))]
+            unsafe {
+                let idx = page / PAGE_SIZE as u32;
+
+                pac::FLASH.cr().modify(|w| {
+                    w.set_per(true);
+                    w.set_pnb(idx as u8);
+                    #[cfg(any(flash_wl, flash_wb))]
+                    w.set_strt(true);
+                    #[cfg(any(flash_l4))]
+                    w.set_start(true);
+                });
+            }
+
+            let ret: Result<(), Error> = self.blocking_wait_ready();
+
+            #[cfg(any(flash_wl, flash_wb, flash_l4))]
+            unsafe {
+                pac::FLASH.cr().modify(|w| w.set_per(false));
+            }
+
+            #[cfg(any(flash_l0, flash_l1))]
+            unsafe {
+                pac::FLASH.pecr().modify(|w| {
+                    w.set_erase(false);
+                    w.set_prog(false);
+                });
+            }
+
+            self.clear_all_err();
+            if ret.is_err() {
+                return ret;
+            }
+        }
+
+        Ok(())
+    }
+
+    fn blocking_wait_ready(&self) -> Result<(), Error> {
+        loop {
+            let sr = unsafe { pac::FLASH.sr().read() };
+
+            if !sr.bsy() {
+                #[cfg(any(flash_wl, flash_wb, flash_l4))]
+                if sr.progerr() {
+                    return Err(Error::Prog);
+                }
+
+                if sr.wrperr() {
+                    return Err(Error::Protected);
+                }
+
+                if sr.pgaerr() {
+                    return Err(Error::Unaligned);
+                }
+
+                if sr.sizerr() {
+                    return Err(Error::Size);
+                }
+
+                #[cfg(any(flash_wl, flash_wb, flash_l4))]
+                if sr.miserr() {
+                    return Err(Error::Miss);
+                }
+
+                #[cfg(any(flash_wl, flash_wb, flash_l4))]
+                if sr.pgserr() {
+                    return Err(Error::Seq);
+                }
+                return Ok(());
+            }
+        }
+    }
+
+    fn clear_all_err(&mut self) {
+        unsafe {
+            pac::FLASH.sr().modify(|w| {
+                #[cfg(any(flash_wl, flash_wb, flash_l4, flash_l0))]
+                if w.rderr() {
+                    w.set_rderr(false);
+                }
+                #[cfg(any(flash_wl, flash_wb, flash_l4))]
+                if w.fasterr() {
+                    w.set_fasterr(false);
+                }
+                #[cfg(any(flash_wl, flash_wb, flash_l4))]
+                if w.miserr() {
+                    w.set_miserr(false);
+                }
+                #[cfg(any(flash_wl, flash_wb, flash_l4))]
+                if w.pgserr() {
+                    w.set_pgserr(false);
+                }
+                if w.sizerr() {
+                    w.set_sizerr(false);
+                }
+                if w.pgaerr() {
+                    w.set_pgaerr(false);
+                }
+                if w.wrperr() {
+                    w.set_wrperr(false);
+                }
+                #[cfg(any(flash_wl, flash_wb, flash_l4))]
+                if w.progerr() {
+                    w.set_progerr(false);
+                }
+                #[cfg(any(flash_wl, flash_wb, flash_l4))]
+                if w.operr() {
+                    w.set_operr(false);
+                }
+            });
+        }
+    }
+}
+
+impl Drop for Flash<'_> {
+    fn drop(&mut self) {
+        self.lock();
+    }
+}
+
+#[derive(Debug, Copy, Clone, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum Error {
+    Prog,
+    Size,
+    Miss,
+    Seq,
+    Protected,
+    Unaligned,
+}
+
+impl<'d> ErrorType for Flash<'d> {
+    type Error = Error;
+}
+
+impl NorFlashError for Error {
+    fn kind(&self) -> NorFlashErrorKind {
+        match self {
+            Self::Size => NorFlashErrorKind::OutOfBounds,
+            Self::Unaligned => NorFlashErrorKind::NotAligned,
+            _ => NorFlashErrorKind::Other,
+        }
+    }
+}
+
+impl<'d> ReadNorFlash for Flash<'d> {
+    const READ_SIZE: usize = WORD_SIZE;
+
+    fn read(&mut self, offset: u32, bytes: &mut [u8]) -> Result<(), Self::Error> {
+        self.blocking_read(offset, bytes)
+    }
+
+    fn capacity(&self) -> usize {
+        FLASH_SIZE
+    }
+}
+
+impl<'d> NorFlash for Flash<'d> {
+    const WRITE_SIZE: usize = WORD_SIZE;
+    const ERASE_SIZE: usize = PAGE_SIZE;
+
+    fn erase(&mut self, from: u32, to: u32) -> Result<(), Self::Error> {
+        self.blocking_erase(from, to)
+    }
+
+    fn write(&mut self, offset: u32, bytes: &[u8]) -> Result<(), Self::Error> {
+        self.blocking_write(offset, bytes)
+    }
+}
+
+/*
+cfg_if::cfg_if! {
+    if #[cfg(feature = "nightly")]
+    {
+        use embedded_storage_async::nor_flash::{AsyncNorFlash, AsyncReadNorFlash};
+        use core::future::Future;
+
+        impl<'d> AsyncNorFlash for Flash<'d> {
+            const WRITE_SIZE: usize = <Self as NorFlash>::WRITE_SIZE;
+            const ERASE_SIZE: usize = <Self as NorFlash>::ERASE_SIZE;
+
+            type WriteFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
+            fn write<'a>(&'a mut self, offset: u32, data: &'a [u8]) -> Self::WriteFuture<'a> {
+                async move {
+                    todo!()
+                }
+            }
+
+            type EraseFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
+            fn erase<'a>(&'a mut self, from: u32, to: u32) -> Self::EraseFuture<'a> {
+                async move {
+                    todo!()
+                }
+            }
+        }
+
+        impl<'d> AsyncReadNorFlash for Flash<'d> {
+            const READ_SIZE: usize = <Self as ReadNorFlash>::READ_SIZE;
+            type ReadFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
+            fn read<'a>(&'a mut self, address: u32, data: &'a mut [u8]) -> Self::ReadFuture<'a> {
+                async move {
+                    todo!()
+                }
+            }
+
+            fn capacity(&self) -> usize {
+                FLASH_SIZE
+            }
+        }
+    }
+}
+*/

embassy-stm32/src/lib.rs

@@ -50,6 +50,8 @@ pub mod i2c;
 
 #[cfg(crc)]
 pub mod crc;
+#[cfg(any(flash_l0, flash_l1, flash_wl, flash_wb, flash_l4))]
+pub mod flash;
 pub mod pwm;
 #[cfg(rng)]
 pub mod rng;

embassy-stm32/src/rcc/wl.rs

@@ -1,4 +1,4 @@
-use crate::pac::RCC;
+use crate::pac::{FLASH, RCC};
 use crate::rcc::{set_freqs, Clocks};
 use crate::time::U32Ext;
 
@@ -15,10 +15,101 @@ pub const HSE32_FREQ: u32 = 32_000_000;
 /// System clock mux source
 #[derive(Clone, Copy)]
 pub enum ClockSrc {
+    MSI(MSIRange),
     HSE32,
     HSI16,
 }
 
+#[derive(Clone, Copy, PartialOrd, PartialEq)]
+pub enum MSIRange {
+    /// Around 100 kHz
+    Range0,
+    /// Around 200 kHz
+    Range1,
+    /// Around 400 kHz
+    Range2,
+    /// Around 800 kHz
+    Range3,
+    /// Around 1 MHz
+    Range4,
+    /// Around 2 MHz
+    Range5,
+    /// Around 4 MHz (reset value)
+    Range6,
+    /// Around 8 MHz
+    Range7,
+    /// Around 16 MHz
+    Range8,
+    /// Around 24 MHz
+    Range9,
+    /// Around 32 MHz
+    Range10,
+    /// Around 48 MHz
+    Range11,
+}
+
+impl MSIRange {
+    fn freq(&self) -> u32 {
+        match self {
+            MSIRange::Range0 => 100_000,
+            MSIRange::Range1 => 200_000,
+            MSIRange::Range2 => 400_000,
+            MSIRange::Range3 => 800_000,
+            MSIRange::Range4 => 1_000_000,
+            MSIRange::Range5 => 2_000_000,
+            MSIRange::Range6 => 4_000_000,
+            MSIRange::Range7 => 8_000_000,
+            MSIRange::Range8 => 16_000_000,
+            MSIRange::Range9 => 24_000_000,
+            MSIRange::Range10 => 32_000_000,
+            MSIRange::Range11 => 48_000_000,
+        }
+    }
+
+    fn vos(&self) -> VoltageScale {
+        if self > &MSIRange::Range8 {
+            VoltageScale::Range1
+        } else {
+            VoltageScale::Range2
+        }
+    }
+}
+
+impl Default for MSIRange {
+    fn default() -> MSIRange {
+        MSIRange::Range6
+    }
+}
+
+impl Into<u8> for MSIRange {
+    fn into(self) -> u8 {
+        match self {
+            MSIRange::Range0 => 0b0000,
+            MSIRange::Range1 => 0b0001,
+            MSIRange::Range2 => 0b0010,
+            MSIRange::Range3 => 0b0011,
+            MSIRange::Range4 => 0b0100,
+            MSIRange::Range5 => 0b0101,
+            MSIRange::Range6 => 0b0110,
+            MSIRange::Range7 => 0b0111,
+            MSIRange::Range8 => 0b1000,
+            MSIRange::Range9 => 0b1001,
+            MSIRange::Range10 => 0b1010,
+            MSIRange::Range11 => 0b1011,
+        }
+    }
+}
+
+/// Voltage Scale
+///
+/// Represents the voltage range feeding the CPU core. The maximum core
+/// clock frequency depends on this value.
+#[derive(Copy, Clone, PartialEq)]
+pub enum VoltageScale {
+    Range1,
+    Range2,
+}
+
 /// AHB prescaler
 #[derive(Clone, Copy, PartialEq)]
 pub enum AHBPrescaler {
@@ -85,6 +176,7 @@ impl Into<u8> for AHBPrescaler {
 pub struct Config {
     pub mux: ClockSrc,
     pub ahb_pre: AHBPrescaler,
+    pub shd_ahb_pre: AHBPrescaler,
     pub apb1_pre: APBPrescaler,
     pub apb2_pre: APBPrescaler,
     pub enable_lsi: bool,
@@ -94,8 +186,9 @@ impl Default for Config {
     #[inline]
     fn default() -> Config {
         Config {
-            mux: ClockSrc::HSI16,
+            mux: ClockSrc::MSI(MSIRange::default()),
             ahb_pre: AHBPrescaler::NotDivided,
+            shd_ahb_pre: AHBPrescaler::NotDivided,
             apb1_pre: APBPrescaler::NotDivided,
             apb2_pre: APBPrescaler::NotDivided,
             enable_lsi: false,
@@ -104,13 +197,13 @@ impl Default for Config {
 }
 
 pub(crate) unsafe fn init(config: Config) {
-    let (sys_clk, sw) = match config.mux {
+    let (sys_clk, sw, vos) = match config.mux {
         ClockSrc::HSI16 => {
             // Enable HSI16
             RCC.cr().write(|w| w.set_hsion(true));
             while !RCC.cr().read().hsirdy() {}
 
-            (HSI_FREQ, 0x01)
+            (HSI_FREQ, 0x01, VoltageScale::Range2)
         }
         ClockSrc::HSE32 => {
             // Enable HSE32
@@ -120,7 +213,17 @@ pub(crate) unsafe fn init(config: Config) {
             });
             while !RCC.cr().read().hserdy() {}
 
-            (HSE32_FREQ, 0x02)
+            (HSE32_FREQ, 0x02, VoltageScale::Range1)
+        }
+        ClockSrc::MSI(range) => {
+            RCC.cr().write(|w| {
+                w.set_msirange(range.into());
+                w.set_msion(true);
+            });
+
+            while !RCC.cr().read().msirdy() {}
+
+            (range.freq(), 0x00, range.vos())
         }
     };
 
@@ -135,6 +238,14 @@ pub(crate) unsafe fn init(config: Config) {
         w.set_ppre2(config.apb2_pre.into());
     });
 
+    RCC.extcfgr().modify(|w| {
+        if config.shd_ahb_pre == AHBPrescaler::NotDivided {
+            w.set_shdhpre(0);
+        } else {
+            w.set_shdhpre(config.shd_ahb_pre.into());
+        }
+    });
+
     let ahb_freq: u32 = match config.ahb_pre {
         AHBPrescaler::NotDivided => sys_clk,
         pre => {
@@ -144,6 +255,15 @@ pub(crate) unsafe fn init(config: Config) {
         }
     };
 
+    let shd_ahb_freq: u32 = match config.shd_ahb_pre {
+        AHBPrescaler::NotDivided => sys_clk,
+        pre => {
+            let pre: u8 = pre.into();
+            let pre = 1 << (pre as u32 - 7);
+            sys_clk / pre
+        }
+    };
+
     let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
         APBPrescaler::NotDivided => (ahb_freq, ahb_freq),
         pre => {
@@ -164,8 +284,7 @@ pub(crate) unsafe fn init(config: Config) {
         }
     };
 
-    // TODO: completely untested
-    let apb3_freq = ahb_freq;
+    let apb3_freq = shd_ahb_freq;
 
     if config.enable_lsi {
         let csr = RCC.csr().read();
@@ -175,11 +294,32 @@ pub(crate) unsafe fn init(config: Config) {
         }
     }
 
+    // Adjust flash latency
+    let flash_clk_src_freq: u32 = shd_ahb_freq;
+    let ws = match vos {
+        VoltageScale::Range1 => match flash_clk_src_freq {
+            0..=18_000_000 => 0b000,
+            18_000_001..=36_000_000 => 0b001,
+            _ => 0b010,
+        },
+        VoltageScale::Range2 => match flash_clk_src_freq {
+            0..=6_000_000 => 0b000,
+            6_000_001..=12_000_000 => 0b001,
+            _ => 0b010,
+        },
+    };
+
+    FLASH.acr().modify(|w| {
+        w.set_latency(ws);
+    });
+
+    while FLASH.acr().read().latency() != ws {}
+
     set_freqs(Clocks {
         sys: sys_clk.hz(),
         ahb1: ahb_freq.hz(),
         ahb2: ahb_freq.hz(),
-        ahb3: ahb_freq.hz(),
+        ahb3: shd_ahb_freq.hz(),
         apb1: apb1_freq.hz(),
         apb2: apb2_freq.hz(),
         apb3: apb3_freq.hz(),