Add stm32 flash + bootloader support
* Add flash drivers for L0, L1, L4, WB and WL. Not tested for WB, but should be similar to WL. * Add embassy-boot-stm32 for bootloading on STM32. * Add flash examples and bootloader examples * Update stm32-data
This commit is contained in:
Ulf Lilleengen
committed by
Ulf Lilleengen
Ulf Lilleengen
parent
9c283cd445
commit
484e0acc63
401
embassy-stm32/src/flash/mod.rs
Normal file
401
embassy-stm32/src/flash/mod.rs
Normal file
@ -0,0 +1,401 @@
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use crate::pac;
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use crate::peripherals::FLASH;
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use core::convert::TryInto;
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use core::marker::PhantomData;
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use core::ptr::write_volatile;
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use embassy::util::Unborrow;
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use embassy_hal_common::unborrow;
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use embedded_storage::nor_flash::{
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ErrorType, NorFlash, NorFlashError, NorFlashErrorKind, ReadNorFlash,
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};
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const FLASH_BASE: usize = 0x8000000;
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#[cfg(flash_l4)]
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mod config {
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use super::*;
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pub(crate) const FLASH_SIZE: usize = 0x100000;
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pub(crate) const FLASH_START: usize = FLASH_BASE;
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pub(crate) const FLASH_END: usize = FLASH_START + FLASH_SIZE;
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pub(crate) const PAGE_SIZE: usize = 2048;
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pub(crate) const WORD_SIZE: usize = 8;
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}
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#[cfg(flash_wb)]
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mod config {
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use super::*;
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pub(crate) const FLASH_SIZE: usize = 0x100000;
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pub(crate) const FLASH_START: usize = FLASH_BASE;
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pub(crate) const FLASH_END: usize = FLASH_START + FLASH_SIZE;
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pub(crate) const PAGE_SIZE: usize = 4096;
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pub(crate) const WORD_SIZE: usize = 8;
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}
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#[cfg(flash_wl)]
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mod config {
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use super::*;
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pub(crate) const FLASH_SIZE: usize = 0x40000;
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pub(crate) const FLASH_START: usize = FLASH_BASE;
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pub(crate) const FLASH_END: usize = FLASH_START + FLASH_SIZE;
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pub(crate) const PAGE_SIZE: usize = 2048;
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pub(crate) const WORD_SIZE: usize = 8;
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}
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#[cfg(flash_l0)]
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mod config {
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use super::*;
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pub(crate) const FLASH_SIZE: usize = 0x30000;
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pub(crate) const FLASH_START: usize = FLASH_BASE;
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pub(crate) const FLASH_END: usize = FLASH_START + FLASH_SIZE;
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pub(crate) const PAGE_SIZE: usize = 128;
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pub(crate) const WORD_SIZE: usize = 4;
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}
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#[cfg(flash_l1)]
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mod config {
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use super::*;
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pub(crate) const FLASH_SIZE: usize = 0x80000;
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pub(crate) const FLASH_START: usize = FLASH_BASE;
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pub(crate) const FLASH_END: usize = FLASH_START + FLASH_SIZE;
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pub(crate) const PAGE_SIZE: usize = 256;
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pub(crate) const WORD_SIZE: usize = 4;
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}
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use config::*;
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pub struct Flash<'d> {
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_inner: FLASH,
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_phantom: PhantomData<&'d mut FLASH>,
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}
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impl<'d> Flash<'d> {
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pub fn new(p: impl Unborrow<Target = FLASH>) -> Self {
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unborrow!(p);
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Self {
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_inner: p,
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_phantom: PhantomData,
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}
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}
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pub fn unlock(p: impl Unborrow<Target = FLASH>) -> Self {
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let flash = Self::new(p);
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#[cfg(any(flash_wl, flash_wb, flash_l4))]
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unsafe {
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pac::FLASH.keyr().write(|w| w.set_keyr(0x4567_0123));
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pac::FLASH.keyr().write(|w| w.set_keyr(0xCDEF_89AB));
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}
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#[cfg(any(flash_l0))]
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unsafe {
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pac::FLASH.pekeyr().write(|w| w.set_pekeyr(0x89ABCDEF));
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pac::FLASH.pekeyr().write(|w| w.set_pekeyr(0x02030405));
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pac::FLASH.prgkeyr().write(|w| w.set_prgkeyr(0x8C9DAEBF));
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pac::FLASH.prgkeyr().write(|w| w.set_prgkeyr(0x13141516));
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}
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flash
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}
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pub fn lock(&mut self) {
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#[cfg(any(flash_wl, flash_wb, flash_l4))]
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unsafe {
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pac::FLASH.cr().modify(|w| w.set_lock(true));
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}
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#[cfg(any(flash_l0))]
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unsafe {
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pac::FLASH.pecr().modify(|w| {
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w.set_optlock(true);
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w.set_prglock(true);
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w.set_pelock(true);
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});
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}
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}
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pub fn blocking_read(&mut self, offset: u32, bytes: &mut [u8]) -> Result<(), Error> {
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if offset as usize >= FLASH_END || offset as usize + bytes.len() > FLASH_END {
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return Err(Error::Size);
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}
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let flash_data = unsafe { core::slice::from_raw_parts(offset as *const u8, bytes.len()) };
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bytes.copy_from_slice(flash_data);
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Ok(())
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}
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pub fn blocking_write(&mut self, offset: u32, buf: &[u8]) -> Result<(), Error> {
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if offset as usize + buf.len() > FLASH_END {
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return Err(Error::Size);
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}
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if offset as usize % WORD_SIZE != 0 || buf.len() as usize % WORD_SIZE != 0 {
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return Err(Error::Unaligned);
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}
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self.clear_all_err();
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#[cfg(any(flash_wl, flash_wb, flash_l4))]
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unsafe {
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pac::FLASH.cr().write(|w| w.set_pg(true));
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}
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let mut ret: Result<(), Error> = Ok(());
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let mut offset = offset;
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for chunk in buf.chunks(WORD_SIZE) {
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for val in chunk.chunks(4) {
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unsafe {
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write_volatile(
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offset as *mut u32,
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u32::from_le_bytes(val[0..4].try_into().unwrap()),
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);
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}
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offset += val.len() as u32;
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}
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ret = self.blocking_wait_ready();
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if ret.is_err() {
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break;
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}
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}
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#[cfg(any(flash_wl, flash_wb, flash_l4))]
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unsafe {
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pac::FLASH.cr().write(|w| w.set_pg(false));
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}
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ret
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}
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pub fn blocking_erase(&mut self, from: u32, to: u32) -> Result<(), Error> {
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if to < from || to as usize > FLASH_END {
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return Err(Error::Size);
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}
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if from as usize % PAGE_SIZE != 0 || to as usize % PAGE_SIZE != 0 {
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return Err(Error::Unaligned);
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}
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self.clear_all_err();
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for page in (from..to).step_by(PAGE_SIZE) {
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#[cfg(any(flash_l0, flash_l1))]
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unsafe {
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pac::FLASH.pecr().modify(|w| {
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w.set_erase(true);
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w.set_prog(true);
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});
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write_volatile(page as *mut u32, 0xFFFFFFFF);
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}
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#[cfg(any(flash_wl, flash_wb, flash_l4))]
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unsafe {
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let idx = page / PAGE_SIZE as u32;
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pac::FLASH.cr().modify(|w| {
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w.set_per(true);
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w.set_pnb(idx as u8);
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#[cfg(any(flash_wl, flash_wb))]
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w.set_strt(true);
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#[cfg(any(flash_l4))]
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w.set_start(true);
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});
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}
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let ret: Result<(), Error> = self.blocking_wait_ready();
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#[cfg(any(flash_wl, flash_wb, flash_l4))]
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unsafe {
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pac::FLASH.cr().modify(|w| w.set_per(false));
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}
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#[cfg(any(flash_l0, flash_l1))]
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unsafe {
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pac::FLASH.pecr().modify(|w| {
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w.set_erase(false);
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w.set_prog(false);
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});
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}
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self.clear_all_err();
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if ret.is_err() {
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return ret;
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}
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}
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Ok(())
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}
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fn blocking_wait_ready(&self) -> Result<(), Error> {
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loop {
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let sr = unsafe { pac::FLASH.sr().read() };
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if !sr.bsy() {
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#[cfg(any(flash_wl, flash_wb, flash_l4))]
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if sr.progerr() {
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return Err(Error::Prog);
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}
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if sr.wrperr() {
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return Err(Error::Protected);
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}
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if sr.pgaerr() {
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return Err(Error::Unaligned);
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}
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if sr.sizerr() {
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return Err(Error::Size);
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}
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#[cfg(any(flash_wl, flash_wb, flash_l4))]
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if sr.miserr() {
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return Err(Error::Miss);
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}
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#[cfg(any(flash_wl, flash_wb, flash_l4))]
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if sr.pgserr() {
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return Err(Error::Seq);
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}
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return Ok(());
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}
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}
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}
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fn clear_all_err(&mut self) {
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unsafe {
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pac::FLASH.sr().modify(|w| {
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#[cfg(any(flash_wl, flash_wb, flash_l4, flash_l0))]
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if w.rderr() {
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w.set_rderr(false);
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}
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#[cfg(any(flash_wl, flash_wb, flash_l4))]
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if w.fasterr() {
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w.set_fasterr(false);
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}
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#[cfg(any(flash_wl, flash_wb, flash_l4))]
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if w.miserr() {
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w.set_miserr(false);
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}
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#[cfg(any(flash_wl, flash_wb, flash_l4))]
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if w.pgserr() {
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w.set_pgserr(false);
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}
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if w.sizerr() {
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w.set_sizerr(false);
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}
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if w.pgaerr() {
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w.set_pgaerr(false);
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}
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if w.wrperr() {
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w.set_wrperr(false);
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}
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#[cfg(any(flash_wl, flash_wb, flash_l4))]
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if w.progerr() {
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w.set_progerr(false);
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}
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#[cfg(any(flash_wl, flash_wb, flash_l4))]
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if w.operr() {
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w.set_operr(false);
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}
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});
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}
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}
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}
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impl Drop for Flash<'_> {
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fn drop(&mut self) {
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self.lock();
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}
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}
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#[derive(Debug, Copy, Clone, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum Error {
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Prog,
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Size,
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Miss,
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Seq,
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Protected,
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Unaligned,
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}
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impl<'d> ErrorType for Flash<'d> {
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type Error = Error;
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}
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impl NorFlashError for Error {
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fn kind(&self) -> NorFlashErrorKind {
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match self {
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Self::Size => NorFlashErrorKind::OutOfBounds,
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Self::Unaligned => NorFlashErrorKind::NotAligned,
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_ => NorFlashErrorKind::Other,
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}
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}
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}
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impl<'d> ReadNorFlash for Flash<'d> {
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const READ_SIZE: usize = WORD_SIZE;
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fn read(&mut self, offset: u32, bytes: &mut [u8]) -> Result<(), Self::Error> {
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self.blocking_read(offset, bytes)
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}
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fn capacity(&self) -> usize {
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FLASH_SIZE
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}
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}
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impl<'d> NorFlash for Flash<'d> {
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const WRITE_SIZE: usize = WORD_SIZE;
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const ERASE_SIZE: usize = PAGE_SIZE;
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fn erase(&mut self, from: u32, to: u32) -> Result<(), Self::Error> {
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self.blocking_erase(from, to)
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}
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fn write(&mut self, offset: u32, bytes: &[u8]) -> Result<(), Self::Error> {
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self.blocking_write(offset, bytes)
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}
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}
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/*
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cfg_if::cfg_if! {
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if #[cfg(feature = "nightly")]
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{
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use embedded_storage_async::nor_flash::{AsyncNorFlash, AsyncReadNorFlash};
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use core::future::Future;
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impl<'d> AsyncNorFlash for Flash<'d> {
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const WRITE_SIZE: usize = <Self as NorFlash>::WRITE_SIZE;
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const ERASE_SIZE: usize = <Self as NorFlash>::ERASE_SIZE;
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type WriteFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
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fn write<'a>(&'a mut self, offset: u32, data: &'a [u8]) -> Self::WriteFuture<'a> {
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async move {
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todo!()
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}
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}
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type EraseFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
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fn erase<'a>(&'a mut self, from: u32, to: u32) -> Self::EraseFuture<'a> {
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async move {
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todo!()
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}
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}
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}
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impl<'d> AsyncReadNorFlash for Flash<'d> {
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const READ_SIZE: usize = <Self as ReadNorFlash>::READ_SIZE;
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type ReadFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
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fn read<'a>(&'a mut self, address: u32, data: &'a mut [u8]) -> Self::ReadFuture<'a> {
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async move {
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todo!()
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}
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}
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fn capacity(&self) -> usize {
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FLASH_SIZE
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}
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}
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}
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}
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*/
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@ -50,6 +50,8 @@ pub mod i2c;
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#[cfg(crc)]
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pub mod crc;
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#[cfg(any(flash_l0, flash_l1, flash_wl, flash_wb, flash_l4))]
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pub mod flash;
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pub mod pwm;
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#[cfg(rng)]
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pub mod rng;
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@ -1,4 +1,4 @@
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use crate::pac::RCC;
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use crate::pac::{FLASH, RCC};
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use crate::rcc::{set_freqs, Clocks};
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use crate::time::U32Ext;
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@ -15,10 +15,101 @@ pub const HSE32_FREQ: u32 = 32_000_000;
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/// System clock mux source
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#[derive(Clone, Copy)]
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pub enum ClockSrc {
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MSI(MSIRange),
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HSE32,
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HSI16,
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}
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#[derive(Clone, Copy, PartialOrd, PartialEq)]
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pub enum MSIRange {
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/// Around 100 kHz
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Range0,
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/// Around 200 kHz
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Range1,
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/// Around 400 kHz
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Range2,
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/// Around 800 kHz
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Range3,
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/// Around 1 MHz
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Range4,
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/// Around 2 MHz
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Range5,
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/// Around 4 MHz (reset value)
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Range6,
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/// Around 8 MHz
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Range7,
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/// Around 16 MHz
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Range8,
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/// Around 24 MHz
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Range9,
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/// Around 32 MHz
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Range10,
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/// Around 48 MHz
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Range11,
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}
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impl MSIRange {
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fn freq(&self) -> u32 {
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match self {
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MSIRange::Range0 => 100_000,
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MSIRange::Range1 => 200_000,
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MSIRange::Range2 => 400_000,
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MSIRange::Range3 => 800_000,
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MSIRange::Range4 => 1_000_000,
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MSIRange::Range5 => 2_000_000,
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MSIRange::Range6 => 4_000_000,
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MSIRange::Range7 => 8_000_000,
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MSIRange::Range8 => 16_000_000,
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MSIRange::Range9 => 24_000_000,
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MSIRange::Range10 => 32_000_000,
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MSIRange::Range11 => 48_000_000,
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}
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}
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fn vos(&self) -> VoltageScale {
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if self > &MSIRange::Range8 {
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VoltageScale::Range1
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} else {
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VoltageScale::Range2
|
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}
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}
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}
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impl Default for MSIRange {
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fn default() -> MSIRange {
|
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MSIRange::Range6
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}
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}
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impl Into<u8> for MSIRange {
|
||||
fn into(self) -> u8 {
|
||||
match self {
|
||||
MSIRange::Range0 => 0b0000,
|
||||
MSIRange::Range1 => 0b0001,
|
||||
MSIRange::Range2 => 0b0010,
|
||||
MSIRange::Range3 => 0b0011,
|
||||
MSIRange::Range4 => 0b0100,
|
||||
MSIRange::Range5 => 0b0101,
|
||||
MSIRange::Range6 => 0b0110,
|
||||
MSIRange::Range7 => 0b0111,
|
||||
MSIRange::Range8 => 0b1000,
|
||||
MSIRange::Range9 => 0b1001,
|
||||
MSIRange::Range10 => 0b1010,
|
||||
MSIRange::Range11 => 0b1011,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// Voltage Scale
|
||||
///
|
||||
/// Represents the voltage range feeding the CPU core. The maximum core
|
||||
/// clock frequency depends on this value.
|
||||
#[derive(Copy, Clone, PartialEq)]
|
||||
pub enum VoltageScale {
|
||||
Range1,
|
||||
Range2,
|
||||
}
|
||||
|
||||
/// AHB prescaler
|
||||
#[derive(Clone, Copy, PartialEq)]
|
||||
pub enum AHBPrescaler {
|
||||
@ -85,6 +176,7 @@ impl Into<u8> for AHBPrescaler {
|
||||
pub struct Config {
|
||||
pub mux: ClockSrc,
|
||||
pub ahb_pre: AHBPrescaler,
|
||||
pub shd_ahb_pre: AHBPrescaler,
|
||||
pub apb1_pre: APBPrescaler,
|
||||
pub apb2_pre: APBPrescaler,
|
||||
pub enable_lsi: bool,
|
||||
@ -94,8 +186,9 @@ impl Default for Config {
|
||||
#[inline]
|
||||
fn default() -> Config {
|
||||
Config {
|
||||
mux: ClockSrc::HSI16,
|
||||
mux: ClockSrc::MSI(MSIRange::default()),
|
||||
ahb_pre: AHBPrescaler::NotDivided,
|
||||
shd_ahb_pre: AHBPrescaler::NotDivided,
|
||||
apb1_pre: APBPrescaler::NotDivided,
|
||||
apb2_pre: APBPrescaler::NotDivided,
|
||||
enable_lsi: false,
|
||||
@ -104,13 +197,13 @@ impl Default for Config {
|
||||
}
|
||||
|
||||
pub(crate) unsafe fn init(config: Config) {
|
||||
let (sys_clk, sw) = match config.mux {
|
||||
let (sys_clk, sw, vos) = match config.mux {
|
||||
ClockSrc::HSI16 => {
|
||||
// Enable HSI16
|
||||
RCC.cr().write(|w| w.set_hsion(true));
|
||||
while !RCC.cr().read().hsirdy() {}
|
||||
|
||||
(HSI_FREQ, 0x01)
|
||||
(HSI_FREQ, 0x01, VoltageScale::Range2)
|
||||
}
|
||||
ClockSrc::HSE32 => {
|
||||
// Enable HSE32
|
||||
@ -120,7 +213,17 @@ pub(crate) unsafe fn init(config: Config) {
|
||||
});
|
||||
while !RCC.cr().read().hserdy() {}
|
||||
|
||||
(HSE32_FREQ, 0x02)
|
||||
(HSE32_FREQ, 0x02, VoltageScale::Range1)
|
||||
}
|
||||
ClockSrc::MSI(range) => {
|
||||
RCC.cr().write(|w| {
|
||||
w.set_msirange(range.into());
|
||||
w.set_msion(true);
|
||||
});
|
||||
|
||||
while !RCC.cr().read().msirdy() {}
|
||||
|
||||
(range.freq(), 0x00, range.vos())
|
||||
}
|
||||
};
|
||||
|
||||
@ -135,6 +238,14 @@ pub(crate) unsafe fn init(config: Config) {
|
||||
w.set_ppre2(config.apb2_pre.into());
|
||||
});
|
||||
|
||||
RCC.extcfgr().modify(|w| {
|
||||
if config.shd_ahb_pre == AHBPrescaler::NotDivided {
|
||||
w.set_shdhpre(0);
|
||||
} else {
|
||||
w.set_shdhpre(config.shd_ahb_pre.into());
|
||||
}
|
||||
});
|
||||
|
||||
let ahb_freq: u32 = match config.ahb_pre {
|
||||
AHBPrescaler::NotDivided => sys_clk,
|
||||
pre => {
|
||||
@ -144,6 +255,15 @@ pub(crate) unsafe fn init(config: Config) {
|
||||
}
|
||||
};
|
||||
|
||||
let shd_ahb_freq: u32 = match config.shd_ahb_pre {
|
||||
AHBPrescaler::NotDivided => sys_clk,
|
||||
pre => {
|
||||
let pre: u8 = pre.into();
|
||||
let pre = 1 << (pre as u32 - 7);
|
||||
sys_clk / pre
|
||||
}
|
||||
};
|
||||
|
||||
let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
|
||||
APBPrescaler::NotDivided => (ahb_freq, ahb_freq),
|
||||
pre => {
|
||||
@ -164,8 +284,7 @@ pub(crate) unsafe fn init(config: Config) {
|
||||
}
|
||||
};
|
||||
|
||||
// TODO: completely untested
|
||||
let apb3_freq = ahb_freq;
|
||||
let apb3_freq = shd_ahb_freq;
|
||||
|
||||
if config.enable_lsi {
|
||||
let csr = RCC.csr().read();
|
||||
@ -175,11 +294,32 @@ pub(crate) unsafe fn init(config: Config) {
|
||||
}
|
||||
}
|
||||
|
||||
// Adjust flash latency
|
||||
let flash_clk_src_freq: u32 = shd_ahb_freq;
|
||||
let ws = match vos {
|
||||
VoltageScale::Range1 => match flash_clk_src_freq {
|
||||
0..=18_000_000 => 0b000,
|
||||
18_000_001..=36_000_000 => 0b001,
|
||||
_ => 0b010,
|
||||
},
|
||||
VoltageScale::Range2 => match flash_clk_src_freq {
|
||||
0..=6_000_000 => 0b000,
|
||||
6_000_001..=12_000_000 => 0b001,
|
||||
_ => 0b010,
|
||||
},
|
||||
};
|
||||
|
||||
FLASH.acr().modify(|w| {
|
||||
w.set_latency(ws);
|
||||
});
|
||||
|
||||
while FLASH.acr().read().latency() != ws {}
|
||||
|
||||
set_freqs(Clocks {
|
||||
sys: sys_clk.hz(),
|
||||
ahb1: ahb_freq.hz(),
|
||||
ahb2: ahb_freq.hz(),
|
||||
ahb3: ahb_freq.hz(),
|
||||
ahb3: shd_ahb_freq.hz(),
|
||||
apb1: apb1_freq.hz(),
|
||||
apb2: apb2_freq.hz(),
|
||||
apb3: apb3_freq.hz(),
|
||||
|
||||
Reference in New Issue
Block a user