From 4a156df7a1e3ed9513cc61cb063d7af86b5cc2fb Mon Sep 17 00:00:00 2001 From: xoviat Date: Sat, 14 Oct 2023 23:33:57 -0500 Subject: [PATCH] stm32: expand rcc mux to g4 and h7 --- embassy-stm32/Cargo.toml | 4 +-- embassy-stm32/build.rs | 43 +++++++++++++----------------- embassy-stm32/src/rcc/g4.rs | 17 ++++++------ embassy-stm32/src/rcc/h.rs | 33 ++++++++++++----------- embassy-stm32/src/rcc/mod.rs | 47 ++++++++++++++++++--------------- examples/stm32g4/src/bin/adc.rs | 2 +- 6 files changed, 72 insertions(+), 74 deletions(-) diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml index b18cafb8..0629bc09 100644 --- a/embassy-stm32/Cargo.toml +++ b/embassy-stm32/Cargo.toml @@ -58,7 +58,7 @@ rand_core = "0.6.3" sdio-host = "0.5.0" embedded-sdmmc = { git = "https://github.com/embassy-rs/embedded-sdmmc-rs", rev = "a4f293d3a6f72158385f79c98634cb8a14d0d2fc", optional = true } critical-section = "1.1" -stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-e6e51db6cdd7d533e52ca7a3237f7816a0486cd4" } +stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-7dafe9d8bbc739be48199185f0caa1582b1da3f7" } vcell = "0.1.3" bxcan = "0.7.0" nb = "1.0.0" @@ -76,7 +76,7 @@ critical-section = { version = "1.1", features = ["std"] } [build-dependencies] proc-macro2 = "1.0.36" quote = "1.0.15" -stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-e6e51db6cdd7d533e52ca7a3237f7816a0486cd4", default-features = false, features = ["metadata"]} +stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-7dafe9d8bbc739be48199185f0caa1582b1da3f7", default-features = false, features = ["metadata"]} [features] diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs index 3e1c76f3..45aad027 100644 --- a/embassy-stm32/build.rs +++ b/embassy-stm32/build.rs @@ -388,20 +388,21 @@ fn main() { }); } + // ======== + // Extract the rcc registers + let rcc_registers = METADATA + .peripherals + .iter() + .filter_map(|p| p.registers.as_ref()) + .find(|r| r.kind == "rcc") + .unwrap(); + // ======== // Generate rcc fieldset and enum maps let rcc_enum_map: HashMap<&str, HashMap<&str, &Enum>> = { - let rcc_registers = METADATA - .peripherals - .iter() - .filter_map(|p| p.registers.as_ref()) - .find(|r| r.kind == "rcc") - .unwrap() - .ir; - - let rcc_blocks = rcc_registers.blocks.iter().find(|b| b.name == "Rcc").unwrap().items; - let rcc_fieldsets: HashMap<&str, &FieldSet> = rcc_registers.fieldsets.iter().map(|f| (f.name, f)).collect(); - let rcc_enums: HashMap<&str, &Enum> = rcc_registers.enums.iter().map(|e| (e.name, e)).collect(); + let rcc_blocks = rcc_registers.ir.blocks.iter().find(|b| b.name == "Rcc").unwrap().items; + let rcc_fieldsets: HashMap<&str, &FieldSet> = rcc_registers.ir.fieldsets.iter().map(|f| (f.name, f)).collect(); + let rcc_enums: HashMap<&str, &Enum> = rcc_registers.ir.enums.iter().map(|e| (e.name, e)).collect(); rcc_blocks .iter() @@ -494,8 +495,10 @@ fn main() { }; let mux_for = |mux: Option<&'static PeripheralRccRegister>| { - // temporary hack to restrict the scope of the implementation to h5 - if !&chip_name.starts_with("stm32h5") { + let checked_rccs = HashSet::from(["h5", "h50", "h7", "h7ab", "h7rm0433", "g4"]); + + // restrict mux implementation to supported versions + if !checked_rccs.contains(rcc_registers.version) { return None; } @@ -518,11 +521,9 @@ fn main() { .filter(|v| v.name != "DISABLE") .map(|v| { let variant_name = format_ident!("{}", v.name); - - // temporary hack to restrict the scope of the implementation until clock names can be stabilized let clock_name = format_ident!("{}", v.name.to_ascii_lowercase()); - if v.name.starts_with("AHB") || v.name.starts_with("APB") { + if v.name.starts_with("AHB") || v.name.starts_with("APB") || v.name == "SYS" { quote! { #enum_name::#variant_name => unsafe { crate::rcc::get_freqs().#clock_name }, } @@ -1013,15 +1014,7 @@ fn main() { // ======== // Generate Div/Mul impls for RCC prescalers/dividers/multipliers. - let rcc_registers = METADATA - .peripherals - .iter() - .filter_map(|p| p.registers.as_ref()) - .find(|r| r.kind == "rcc") - .unwrap() - .ir; - - for e in rcc_registers.enums { + for e in rcc_registers.ir.enums { fn is_rcc_name(e: &str) -> bool { match e { "Pllp" | "Pllq" | "Pllr" | "Pllm" | "Plln" => true, diff --git a/embassy-stm32/src/rcc/g4.rs b/embassy-stm32/src/rcc/g4.rs index afdf5cc7..581bf9e0 100644 --- a/embassy-stm32/src/rcc/g4.rs +++ b/embassy-stm32/src/rcc/g4.rs @@ -119,8 +119,8 @@ impl Default for Config { low_power_run: false, pll: None, clock_48mhz_src: None, - adc12_clock_source: Adcsel::NOCLK, - adc345_clock_source: Adcsel::NOCLK, + adc12_clock_source: Adcsel::DISABLE, + adc345_clock_source: Adcsel::DISABLE, ls: Default::default(), } } @@ -326,16 +326,16 @@ pub(crate) unsafe fn init(config: Config) { RCC.ccipr().modify(|w| w.set_adc345sel(config.adc345_clock_source)); let adc12_ck = match config.adc12_clock_source { - AdcClockSource::NOCLK => None, - AdcClockSource::PLLP => pll_freq.as_ref().unwrap().pll_p, - AdcClockSource::SYSCLK => Some(sys_clk), + AdcClockSource::DISABLE => None, + AdcClockSource::PLL1_P => pll_freq.as_ref().unwrap().pll_p, + AdcClockSource::SYS => Some(sys_clk), _ => unreachable!(), }; let adc345_ck = match config.adc345_clock_source { - AdcClockSource::NOCLK => None, - AdcClockSource::PLLP => pll_freq.as_ref().unwrap().pll_p, - AdcClockSource::SYSCLK => Some(sys_clk), + AdcClockSource::DISABLE => None, + AdcClockSource::PLL1_P => pll_freq.as_ref().unwrap().pll_p, + AdcClockSource::SYS => Some(sys_clk), _ => unreachable!(), }; @@ -356,6 +356,7 @@ pub(crate) unsafe fn init(config: Config) { apb2_tim: apb2_tim_freq, adc: adc12_ck, adc34: adc345_ck, + pll1_p: None, rtc, }); } diff --git a/embassy-stm32/src/rcc/h.rs b/embassy-stm32/src/rcc/h.rs index 9132df7e..bbbbc9c1 100644 --- a/embassy-stm32/src/rcc/h.rs +++ b/embassy-stm32/src/rcc/h.rs @@ -446,7 +446,7 @@ pub(crate) unsafe fn init(config: Config) { #[cfg(stm32h5)] let adc = match config.adc_clock_source { AdcClockSource::HCLK => Some(hclk), - AdcClockSource::SYSCLK => Some(sys), + AdcClockSource::SYS => Some(sys), AdcClockSource::PLL2_R => pll2.r, AdcClockSource::HSE => hse, AdcClockSource::HSI => hsi, @@ -540,36 +540,34 @@ pub(crate) unsafe fn init(config: Config) { adc, rtc, - #[cfg(stm32h5)] + #[cfg(any(stm32h5, stm32h7))] hsi: None, #[cfg(stm32h5)] hsi48: None, #[cfg(stm32h5)] lsi: None, - #[cfg(stm32h5)] + #[cfg(any(stm32h5, stm32h7))] csi: None, - #[cfg(stm32h5)] + #[cfg(any(stm32h5, stm32h7))] lse: None, - #[cfg(stm32h5)] + #[cfg(any(stm32h5, stm32h7))] hse: None, - #[cfg(stm32h5)] + #[cfg(any(stm32h5, stm32h7))] pll1_q: pll1.q, - #[cfg(stm32h5)] - pll2_q: pll2.q, - #[cfg(stm32h5)] + #[cfg(any(stm32h5, stm32h7))] pll2_p: pll2.p, - #[cfg(stm32h5)] + #[cfg(any(stm32h5, stm32h7))] + pll2_q: pll2.q, + #[cfg(any(stm32h5, stm32h7))] pll2_r: pll2.r, - #[cfg(rcc_h5)] + #[cfg(any(rcc_h5, stm32h7))] pll3_p: pll3.p, - #[cfg(rcc_h5)] + #[cfg(any(rcc_h5, stm32h7))] pll3_q: pll3.q, - #[cfg(rcc_h5)] + #[cfg(any(rcc_h5, stm32h7))] pll3_r: pll3.r, - #[cfg(stm32h5)] - pll3_1: None, #[cfg(rcc_h50)] pll3_p: None, @@ -580,8 +578,11 @@ pub(crate) unsafe fn init(config: Config) { #[cfg(stm32h5)] audioclk: None, - #[cfg(stm32h5)] + #[cfg(any(stm32h5, stm32h7))] per: None, + + #[cfg(stm32h7)] + rcc_pclk_d3: None, }); } diff --git a/embassy-stm32/src/rcc/mod.rs b/embassy-stm32/src/rcc/mod.rs index 0904ddbd..1603a2c3 100644 --- a/embassy-stm32/src/rcc/mod.rs +++ b/embassy-stm32/src/rcc/mod.rs @@ -113,6 +113,23 @@ pub struct Clocks { #[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))] pub pllsai: Option, + #[cfg(stm32g4)] + pub pll1_p: Option, + #[cfg(any(stm32h5, stm32h7))] + pub pll1_q: Option, + #[cfg(any(stm32h5, stm32h7))] + pub pll2_q: Option, + #[cfg(any(stm32h5, stm32h7))] + pub pll2_p: Option, + #[cfg(any(stm32h5, stm32h7))] + pub pll2_r: Option, + #[cfg(any(stm32h5, stm32h7))] + pub pll3_p: Option, + #[cfg(any(stm32h5, stm32h7))] + pub pll3_q: Option, + #[cfg(any(stm32h5, stm32h7))] + pub pll3_r: Option, + #[cfg(any( rcc_f1, rcc_f100, @@ -135,41 +152,27 @@ pub struct Clocks { pub rtc: Option, - #[cfg(stm32h5)] + #[cfg(any(stm32h5, stm32h7))] pub hsi: Option, #[cfg(stm32h5)] pub hsi48: Option, #[cfg(stm32h5)] pub lsi: Option, - #[cfg(stm32h5)] + #[cfg(any(stm32h5, stm32h7))] pub csi: Option, - #[cfg(stm32h5)] + #[cfg(any(stm32h5, stm32h7))] pub lse: Option, - #[cfg(stm32h5)] + #[cfg(any(stm32h5, stm32h7))] pub hse: Option, - #[cfg(stm32h5)] - pub pll1_q: Option, - #[cfg(stm32h5)] - pub pll2_q: Option, - #[cfg(stm32h5)] - pub pll2_p: Option, - #[cfg(stm32h5)] - pub pll2_r: Option, - #[cfg(stm32h5)] - pub pll3_p: Option, - #[cfg(stm32h5)] - pub pll3_q: Option, - #[cfg(stm32h5)] - pub pll3_r: Option, - #[cfg(stm32h5)] - pub pll3_1: Option, - #[cfg(stm32h5)] pub audioclk: Option, - #[cfg(stm32h5)] + #[cfg(any(stm32h5, stm32h7))] pub per: Option, + + #[cfg(stm32h7)] + pub rcc_pclk_d3: Option, } #[cfg(feature = "low-power")] diff --git a/examples/stm32g4/src/bin/adc.rs b/examples/stm32g4/src/bin/adc.rs index 9daf4e4c..db7f6ecb 100644 --- a/examples/stm32g4/src/bin/adc.rs +++ b/examples/stm32g4/src/bin/adc.rs @@ -24,7 +24,7 @@ async fn main(_spawner: Spawner) { div_r: Some(PllR::DIV2), }); - config.rcc.adc12_clock_source = AdcClockSource::SYSCLK; + config.rcc.adc12_clock_source = AdcClockSource::SYS; config.rcc.mux = ClockSrc::PLL; let mut p = embassy_stm32::init(config);