stm32/rtc: build more chips

embassy-stm32/src/lib.rs

@@ -49,7 +49,7 @@ pub mod pwm;
 pub mod qspi;
 #[cfg(rng)]
 pub mod rng;
-#[cfg(all(rtc, not(any(rtc_v1, rtc_v2f0, rtc_v2f7, rtc_v3, rtc_v3u5))))]
+#[cfg(all(rtc, not(rtc_v1)))]
 pub mod rtc;
 #[cfg(sdmmc)]
 pub mod sdmmc;

embassy-stm32/src/rtc/v2.rs

@@ -9,7 +9,70 @@ impl<'d, T: Instance> super::Rtc<'d, T> {
     pub(super) fn apply_config(&mut self, rtc_config: RtcConfig) {
         // Unlock the backup domain
         unsafe {
-            unlock_backup_domain(rtc_config.clock_config as u8);
+            let clock_config = rtc_config.clock_config as u8;
+
+            #[cfg(not(rtc_v2wb))]
+            use stm32_metapac::rcc::vals::Rtcsel;
+
+            #[cfg(any(rtc_v2f2, rtc_v2f3, rtc_v2l1))]
+            let cr = crate::pac::PWR.cr();
+            #[cfg(any(rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l4, rtc_v2wb))]
+            let cr = crate::pac::PWR.cr1();
+
+            // TODO: Missing from PAC for l0 and f0?
+            #[cfg(not(any(rtc_v2f0, rtc_v2l0)))]
+            {
+                cr.modify(|w| w.set_dbp(true));
+                while !cr.read().dbp() {}
+            }
+
+            #[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
+            let reg = crate::pac::RCC.bdcr().read();
+            #[cfg(any(rtc_v2l0, rtc_v2l1))]
+            let reg = crate::pac::RCC.csr().read();
+
+            #[cfg(any(rtc_v2h7, rtc_v2l4, rtc_v2wb))]
+            assert!(!reg.lsecsson(), "RTC is not compatible with LSE CSS, yet.");
+
+            #[cfg(rtc_v2wb)]
+            let rtcsel = reg.rtcsel();
+            #[cfg(not(rtc_v2wb))]
+            let rtcsel = reg.rtcsel().0;
+
+            if !reg.rtcen() || rtcsel != clock_config {
+                #[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
+                crate::pac::RCC.bdcr().modify(|w| w.set_bdrst(true));
+
+                #[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
+                let cr = crate::pac::RCC.bdcr();
+                #[cfg(any(rtc_v2l0, rtc_v2l1))]
+                let cr = crate::pac::RCC.csr();
+
+                cr.modify(|w| {
+                    // Reset
+                    #[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
+                    w.set_bdrst(false);
+
+                    // Select RTC source
+                    #[cfg(not(rtc_v2wb))]
+                    w.set_rtcsel(Rtcsel(clock_config));
+                    #[cfg(rtc_v2wb)]
+                    w.set_rtcsel(clock_config);
+                    w.set_rtcen(true);
+
+                    // Restore bcdr
+                    #[cfg(any(rtc_v2l4, rtc_v2wb))]
+                    w.set_lscosel(reg.lscosel());
+                    #[cfg(any(rtc_v2l4, rtc_v2wb))]
+                    w.set_lscoen(reg.lscoen());
+
+                    w.set_lseon(reg.lseon());
+
+                    #[cfg(any(rtc_v2f0, rtc_v2f7, rtc_v2h7, rtc_v2l4, rtc_v2wb))]
+                    w.set_lsedrv(reg.lsedrv());
+                    w.set_lsebyp(reg.lsebyp());
+                });
+            }
         }
 
         self.write(true, |rtc| unsafe {
@@ -157,7 +220,7 @@ pub fn write_backup_register(rtc: &Rtc, register: usize, value: u32) {
 }
 
 pub(crate) unsafe fn enable_peripheral_clk() {
-    #[cfg(any(rtc_v2f0, rtc_v2f7, rtc_v2l4, rtc_v2wb))]
+    #[cfg(any(rtc_v2l4, rtc_v2wb))]
     {
         // enable peripheral clock for communication
         crate::pac::RCC.apb1enr1().modify(|w| w.set_rtcapben(true));
@@ -168,68 +231,3 @@ pub(crate) unsafe fn enable_peripheral_clk() {
 }
 
 pub const BACKUP_REGISTER_COUNT: usize = 20;
-
-pub(super) unsafe fn unlock_backup_domain(clock_config: u8) {
-    #[cfg(not(rtc_v2wb))]
-    use stm32_metapac::rcc::vals::Rtcsel;
-
-    #[cfg(any(rtc_v2f2, rtc_v2f3, rtc_v2l1))]
-    let cr = crate::pac::PWR.cr();
-    #[cfg(any(rtc_v2f0, rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l4, rtc_v2wb))]
-    let cr = crate::pac::PWR.cr1();
-
-    // TODO: Missing from PAC for l0?
-    #[cfg(not(rtc_v2l0))]
-    {
-        cr.modify(|w| w.set_dbp(true));
-        while !cr.read().dbp() {}
-    }
-
-    #[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
-    let reg = crate::pac::RCC.bdcr().read();
-    #[cfg(any(rtc_v2l0, rtc_v2l1))]
-    let reg = crate::pac::RCC.csr().read();
-
-    #[cfg(any(rtc_v2f0, rtc_v2f7, rtc_v2h7, rtc_v2l4, rtc_v2wb))]
-    assert!(!reg.lsecsson(), "RTC is not compatible with LSE CSS, yet.");
-
-    #[cfg(rtc_v2wb)]
-    let rtcsel = reg.rtcsel();
-    #[cfg(not(rtc_v2wb))]
-    let rtcsel = reg.rtcsel().0;
-
-    if !reg.rtcen() || rtcsel != clock_config {
-        #[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
-        crate::pac::RCC.bdcr().modify(|w| w.set_bdrst(true));
-
-        #[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
-        let cr = crate::pac::RCC.bdcr();
-        #[cfg(any(rtc_v2l0, rtc_v2l1))]
-        let cr = crate::pac::RCC.csr();
-
-        cr.modify(|w| {
-            // Reset
-            #[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
-            w.set_bdrst(false);
-
-            // Select RTC source
-            #[cfg(not(rtc_v2wb))]
-            w.set_rtcsel(Rtcsel(clock_config));
-            #[cfg(rtc_v2wb)]
-            w.set_rtcsel(clock_config);
-            w.set_rtcen(true);
-
-            // Restore bcdr
-            #[cfg(any(rtc_v2f0, rtc_v2f7, rtc_v2l4, rtc_v2wb))]
-            w.set_lscosel(reg.lscosel());
-            #[cfg(any(rtc_v2f0, rtc_v2f7, rtc_v2l4, rtc_v2wb))]
-            w.set_lscoen(reg.lscoen());
-
-            w.set_lseon(reg.lseon());
-
-            #[cfg(any(rtc_v2f0, rtc_v2f7, rtc_v2h7, rtc_v2l4, rtc_v2wb))]
-            w.set_lsedrv(reg.lsedrv());
-            w.set_lsebyp(reg.lsebyp());
-        });
-    }
-}

embassy-stm32/src/rtc/v3.rs

@@ -9,43 +9,30 @@ impl<'d, T: Instance> super::Rtc<'d, T> {
     pub(super) fn apply_config(&mut self, rtc_config: RtcConfig) {
         // Unlock the backup domain
         unsafe {
-            #[cfg(feature = "stm32g0c1ve")]
+            #[cfg(any(rtc_v3u5, rcc_g0))]
+            use crate::pac::rcc::vals::Rtcsel;
+            #[cfg(not(any(rtc_v3u5, rcc_g0, rcc_g4, rcc_wl5, rcc_wle)))]
+            use crate::pac::rtc::vals::Rtcsel;
+
+            #[cfg(not(any(rtc_v3u5, rcc_wl5, rcc_wle)))]
             {
                 crate::pac::PWR.cr1().modify(|w| w.set_dbp(true));
                 while !crate::pac::PWR.cr1().read().dbp() {}
             }
-
+            #[cfg(any(rcc_wl5, rcc_wle))]
-            #[cfg(not(any(
-                feature = "stm32g0c1ve",
-                feature = "stm32g491re",
-                feature = "stm32u585zi",
-                feature = "stm32g473cc"
-            )))]
             {
-                crate::pac::PWR
+                use crate::pac::pwr::vals::Dbp;
-                    .cr1()
+
-                    .modify(|w| w.set_dbp(stm32_metapac::pwr::vals::Dbp::ENABLED));
+                crate::pac::PWR.cr1().modify(|w| w.set_dbp(Dbp::ENABLED));
-                while crate::pac::PWR.cr1().read().dbp() != stm32_metapac::pwr::vals::Dbp::DISABLED {}
+                while crate::pac::PWR.cr1().read().dbp() != Dbp::ENABLED {}
             }
 
             let reg = crate::pac::RCC.bdcr().read();
             assert!(!reg.lsecsson(), "RTC is not compatible with LSE CSS, yet.");
 
             let config_rtcsel = rtc_config.clock_config as u8;
-            #[cfg(not(any(
+            #[cfg(not(any(rcc_wl5, rcc_wle, rcc_g4)))]
-                feature = "stm32wl54jc-cm0p",
+            let config_rtcsel = Rtcsel(config_rtcsel);
-                feature = "stm32wle5ub",
-                feature = "stm32g0c1ve",
-                feature = "stm32wl55jc-cm4",
-                feature = "stm32wl55uc-cm4",
-                feature = "stm32g491re",
-                feature = "stm32g473cc",
-                feature = "stm32u585zi",
-                feature = "stm32wle5jb"
-            )))]
-            let config_rtcsel = stm32_metapac::rtc::vals::Rtcsel(config_rtcsel);
-            #[cfg(feature = "stm32g0c1ve")]
-            let config_rtcsel = stm32_metapac::rcc::vals::Rtcsel(config_rtcsel);
 
             if !reg.rtcen() || reg.rtcsel() != config_rtcsel {
                 crate::pac::RCC.bdcr().modify(|w| w.set_bdrst(true));