stm32/rcc: consistent casing and naming for PLL enums.
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@ -35,7 +35,7 @@ impl Default for ClockSrc {
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#[derive(Clone, Copy)]
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pub struct PllConfig {
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/// The clock source for the PLL.
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pub source: PllSrc,
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pub source: PllSource,
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/// The PLL prescaler.
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///
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/// The clock speed of the `source` divided by `m` must be between 4 and 16 MHz.
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@ -57,7 +57,7 @@ impl PllConfig {
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/// A configuration for HSI / 1 * 10 / 1 = 160 MHz
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pub const fn hsi_160mhz() -> Self {
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PllConfig {
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source: PllSrc::HSI,
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source: PllSource::HSI,
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m: Pllm::DIV1,
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n: Plln::MUL10,
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r: Plldiv::DIV1,
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@ -67,7 +67,7 @@ impl PllConfig {
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/// A configuration for MSIS @ 48 MHz / 3 * 10 / 1 = 160 MHz
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pub const fn msis_160mhz() -> Self {
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PllConfig {
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source: PllSrc::MSIS(Msirange::RANGE_48MHZ),
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source: PllSource::MSIS(Msirange::RANGE_48MHZ),
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m: Pllm::DIV3,
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n: Plln::MUL10,
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r: Plldiv::DIV1,
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@ -76,7 +76,7 @@ impl PllConfig {
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}
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#[derive(Clone, Copy)]
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pub enum PllSrc {
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pub enum PllSource {
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/// Use an internal medium speed oscillator as the PLL source.
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MSIS(Msirange),
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/// Use the external high speed clock as the system PLL source.
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@ -88,12 +88,12 @@ pub enum PllSrc {
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HSI,
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}
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impl Into<Pllsrc> for PllSrc {
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impl Into<Pllsrc> for PllSource {
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fn into(self) -> Pllsrc {
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match self {
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PllSrc::MSIS(..) => Pllsrc::MSIS,
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PllSrc::HSE(..) => Pllsrc::HSE,
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PllSrc::HSI => Pllsrc::HSI,
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PllSource::MSIS(..) => Pllsrc::MSIS,
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PllSource::HSE(..) => Pllsrc::HSE,
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PllSource::HSI => Pllsrc::HSI,
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}
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}
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}
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@ -216,9 +216,9 @@ pub(crate) unsafe fn init(config: Config) {
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ClockSrc::PLL1_R(pll) => {
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// Configure the PLL source
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let source_clk = match pll.source {
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PllSrc::MSIS(range) => config.init_msis(range),
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PllSrc::HSE(hertz) => config.init_hse(hertz),
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PllSrc::HSI => config.init_hsi(),
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PllSource::MSIS(range) => config.init_msis(range),
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PllSource::HSE(hertz) => config.init_hse(hertz),
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PllSource::HSI => config.init_hsi(),
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};
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// Calculate the reference clock, which is the source divided by m
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