stm32/rcc: consistent casing and naming for PLL enums.
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		@@ -44,7 +44,7 @@ async fn main(_spawner: Spawner) {
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        });
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        config.rcc.mux = ClockSrc::PLL1_R;
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        config.rcc.pll = Some(Pll {
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            source: PLLSource::HSE,
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            source: PllSource::HSE,
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            prediv: PllPreDiv::DIV2,
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            mul: PllMul::MUL6,
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            divp: None,
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@@ -37,7 +37,7 @@ async fn main(_spawner: Spawner) {
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        });
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        config.rcc.mux = ClockSrc::PLL1_R;
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        config.rcc.pll = Some(Pll {
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            source: PLLSource::HSE,
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            source: PllSource::HSE,
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            prediv: PllPreDiv::DIV2,
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            mul: PllMul::MUL6,
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            divp: None,
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@@ -37,7 +37,7 @@ async fn main(_spawner: Spawner) {
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        });
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        config.rcc.mux = ClockSrc::PLL1_R;
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        config.rcc.pll = Some(Pll {
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            source: PLLSource::HSE,
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            source: PllSource::HSE,
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            prediv: PllPreDiv::DIV2,
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            mul: PllMul::MUL6,
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            divp: None,
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@@ -25,7 +25,7 @@ async fn main(_spawner: Spawner) {
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        });
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        config.rcc.mux = ClockSrc::PLL1_R;
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        config.rcc.pll = Some(Pll {
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            source: PLLSource::HSE,
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            source: PllSource::HSE,
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            prediv: PllPreDiv::DIV2,
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            mul: PllMul::MUL6,
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            divp: None,
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@@ -24,7 +24,7 @@ async fn main(_spawner: Spawner) {
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        });
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        config.rcc.mux = ClockSrc::PLL1_R;
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        config.rcc.pll = Some(Pll {
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            source: PLLSource::HSE,
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            source: PllSource::HSE,
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            prediv: PllPreDiv::DIV2,
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            mul: PllMul::MUL6,
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            divp: None,
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