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PPLXTPRE is a bool.

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This flag for example permits the following clock tree
configuration on stm32f103r8

    let mut config = Config::default();
    config.rcc.hse = Some(Hertz(16_000_000));
    config.rcc.sys_ck = Some(Hertz(72_000_000));
    config.rcc.pclk1 = Some(Hertz(36_000_000));
    config.rcc.pclk2 = Some(Hertz(72_000_000));
    config.rcc.pllxtpre = true;

Init fails if pllxtpre is false.
This commit is contained in:
Marco Pastrello 2023-05-04 22:59:52 +02:00
parent 1cc61dc68a
commit 5158014f3f
1 changed files with 3 additions and 6 deletions
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9
embassy-stm32/src/rcc/f1.rs
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@ -24,14 +24,11 @@ pub struct Config {
pub pclk1: Option<Hertz>, pub pclk1: Option<Hertz>,
pub pclk2: Option<Hertz>, pub pclk2: Option<Hertz>,
pub adcclk: Option<Hertz>, pub adcclk: Option<Hertz>,
pub pllxtpre: Option<bool>, pub pllxtpre: bool,
} }
pub(crate) unsafe fn init(config: Config) { pub(crate) unsafe fn init(config: Config) {
let pllsrcclk = config.hse.map(|hse| hse.0 / match config.pllxtpre { let pllsrcclk = config.hse.map(|hse| hse.0 / if config.pllxtpre {2} else {1}).unwrap_or(HSI_FREQ.0 / 2);
Some(b) => if b {2} else {1},
None => {1},
}).unwrap_or(HSI_FREQ.0 / 2);
let sysclk = config.sys_ck.map(|sys| sys.0).unwrap_or(pllsrcclk); let sysclk = config.sys_ck.map(|sys| sys.0).unwrap_or(pllsrcclk);
let pllmul = sysclk / pllsrcclk; let pllmul = sysclk / pllsrcclk;
@ -148,7 +145,7 @@ pub(crate) unsafe fn init(config: Config) {
} }
if let Some(pllmul_bits) = pllmul_bits { if let Some(pllmul_bits) = pllmul_bits {
RCC.cfgr().modify(|w| w.set_pllxtpre(Pllxtpre(config.pllxtpre.is_some() as u8))); RCC.cfgr().modify(|w| w.set_pllxtpre(Pllxtpre(if config.pllxtpre {1u8} else {0u8})));
// enable PLL and wait for it to be ready // enable PLL and wait for it to be ready
RCC.cfgr().modify(|w| { RCC.cfgr().modify(|w| {
w.set_pllmul(Pllmul(pllmul_bits)); w.set_pllmul(Pllmul(pllmul_bits));