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usb: centralize all control logging in control.rs

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This commit is contained in:
Dario Nieuwenhuis
2022-04-02 04:53:42 +02:00
parent d7d199f2ac
commit 522a87ae42
3 changed files with 17 additions and 13 deletions
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16
embassy-usb/src/control.rs
View File

@ -231,6 +231,8 @@ impl<C: driver::ControlPipe> ControlPipe<C> {
pub(crate) async fn setup(&mut self) -> Setup {
let req = self.control.setup().await;
trace!("control request: {:02x}", req);
match (req.direction, req.length) {
(UsbDirection::Out, n) => Setup::DataOut(
req,
@ -267,15 +269,21 @@ impl<C: driver::ControlPipe> ControlPipe<C> {
}
}
Ok((&buf[0..total], StatusStage {}))
let res = &buf[0..total];
#[cfg(feature = "defmt")]
trace!(" control out data: {:02x}", buf);
#[cfg(not(feature = "defmt"))]
trace!(" control out data: {:02x?}", buf);
Ok((res, StatusStage {}))
}
}
pub(crate) async fn accept_in(&mut self, buf: &[u8], stage: DataInStage) {
#[cfg(feature = "defmt")]
debug!("control in accept {:x}", buf);
trace!(" control in accept {:02x}", buf);
#[cfg(not(feature = "defmt"))]
debug!("control in accept {:x?}", buf);
trace!(" control in accept {:02x?}", buf);
let req_len = stage.length;
let len = buf.len().min(req_len);
@ -305,10 +313,12 @@ impl<C: driver::ControlPipe> ControlPipe<C> {
}
pub(crate) fn accept(&mut self, _: StatusStage) {
trace!(" control accept");
self.control.accept();
}
pub(crate) fn reject(&mut self) {
trace!(" control reject");
self.control.reject();
}
}

12
embassy-usb/src/lib.rs
View File

@ -128,14 +128,10 @@ impl<'d, D: Driver<'d>> UsbDevice<'d, D> {
self.device_state = UsbDeviceState::Suspend;
}
},
Either::Right(req) => {
debug!("control request: {:x}", req);
match req {
Setup::DataIn(req, stage) => self.handle_control_in(req, stage).await,
Setup::DataOut(req, stage) => self.handle_control_out(req, stage).await,
}
}
Either::Right(req) => match req {
Setup::DataIn(req, stage) => self.handle_control_in(req, stage).await,
Setup::DataOut(req, stage) => self.handle_control_out(req, stage).await,
},
}
}
}