usb: centralize all control logging in control.rs

This commit is contained in:
Dario Nieuwenhuis 2022-04-02 04:53:42 +02:00
parent d7d199f2ac
commit 522a87ae42
3 changed files with 17 additions and 13 deletions

View File

@ -615,14 +615,12 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
} }
fn accept(&mut self) { fn accept(&mut self) {
debug!("control accept");
let regs = T::regs(); let regs = T::regs();
regs.tasks_ep0status regs.tasks_ep0status
.write(|w| w.tasks_ep0status().bit(true)); .write(|w| w.tasks_ep0status().bit(true));
} }
fn reject(&mut self) { fn reject(&mut self) {
debug!("control reject");
let regs = T::regs(); let regs = T::regs();
regs.tasks_ep0stall.write(|w| w.tasks_ep0stall().bit(true)); regs.tasks_ep0stall.write(|w| w.tasks_ep0stall().bit(true));
} }

View File

@ -231,6 +231,8 @@ impl<C: driver::ControlPipe> ControlPipe<C> {
pub(crate) async fn setup(&mut self) -> Setup { pub(crate) async fn setup(&mut self) -> Setup {
let req = self.control.setup().await; let req = self.control.setup().await;
trace!("control request: {:02x}", req);
match (req.direction, req.length) { match (req.direction, req.length) {
(UsbDirection::Out, n) => Setup::DataOut( (UsbDirection::Out, n) => Setup::DataOut(
req, req,
@ -267,15 +269,21 @@ impl<C: driver::ControlPipe> ControlPipe<C> {
} }
} }
Ok((&buf[0..total], StatusStage {})) let res = &buf[0..total];
#[cfg(feature = "defmt")]
trace!(" control out data: {:02x}", buf);
#[cfg(not(feature = "defmt"))]
trace!(" control out data: {:02x?}", buf);
Ok((res, StatusStage {}))
} }
} }
pub(crate) async fn accept_in(&mut self, buf: &[u8], stage: DataInStage) { pub(crate) async fn accept_in(&mut self, buf: &[u8], stage: DataInStage) {
#[cfg(feature = "defmt")] #[cfg(feature = "defmt")]
debug!("control in accept {:x}", buf); trace!(" control in accept {:02x}", buf);
#[cfg(not(feature = "defmt"))] #[cfg(not(feature = "defmt"))]
debug!("control in accept {:x?}", buf); trace!(" control in accept {:02x?}", buf);
let req_len = stage.length; let req_len = stage.length;
let len = buf.len().min(req_len); let len = buf.len().min(req_len);
@ -305,10 +313,12 @@ impl<C: driver::ControlPipe> ControlPipe<C> {
} }
pub(crate) fn accept(&mut self, _: StatusStage) { pub(crate) fn accept(&mut self, _: StatusStage) {
trace!(" control accept");
self.control.accept(); self.control.accept();
} }
pub(crate) fn reject(&mut self) { pub(crate) fn reject(&mut self) {
trace!(" control reject");
self.control.reject(); self.control.reject();
} }
} }

View File

@ -128,14 +128,10 @@ impl<'d, D: Driver<'d>> UsbDevice<'d, D> {
self.device_state = UsbDeviceState::Suspend; self.device_state = UsbDeviceState::Suspend;
} }
}, },
Either::Right(req) => { Either::Right(req) => match req {
debug!("control request: {:x}", req); Setup::DataIn(req, stage) => self.handle_control_in(req, stage).await,
Setup::DataOut(req, stage) => self.handle_control_out(req, stage).await,
match req { },
Setup::DataIn(req, stage) => self.handle_control_in(req, stage).await,
Setup::DataOut(req, stage) => self.handle_control_out(req, stage).await,
}
}
} }
} }
} }