usb: centralize all control logging in control.rs
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d7d199f2ac
commit
522a87ae42
@ -615,14 +615,12 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
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}
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}
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fn accept(&mut self) {
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fn accept(&mut self) {
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debug!("control accept");
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let regs = T::regs();
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let regs = T::regs();
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regs.tasks_ep0status
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regs.tasks_ep0status
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.write(|w| w.tasks_ep0status().bit(true));
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.write(|w| w.tasks_ep0status().bit(true));
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}
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}
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fn reject(&mut self) {
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fn reject(&mut self) {
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debug!("control reject");
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let regs = T::regs();
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let regs = T::regs();
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regs.tasks_ep0stall.write(|w| w.tasks_ep0stall().bit(true));
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regs.tasks_ep0stall.write(|w| w.tasks_ep0stall().bit(true));
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}
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}
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@ -231,6 +231,8 @@ impl<C: driver::ControlPipe> ControlPipe<C> {
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pub(crate) async fn setup(&mut self) -> Setup {
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pub(crate) async fn setup(&mut self) -> Setup {
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let req = self.control.setup().await;
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let req = self.control.setup().await;
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trace!("control request: {:02x}", req);
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match (req.direction, req.length) {
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match (req.direction, req.length) {
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(UsbDirection::Out, n) => Setup::DataOut(
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(UsbDirection::Out, n) => Setup::DataOut(
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req,
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req,
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@ -267,15 +269,21 @@ impl<C: driver::ControlPipe> ControlPipe<C> {
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}
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}
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}
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}
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Ok((&buf[0..total], StatusStage {}))
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let res = &buf[0..total];
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#[cfg(feature = "defmt")]
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trace!(" control out data: {:02x}", buf);
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#[cfg(not(feature = "defmt"))]
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trace!(" control out data: {:02x?}", buf);
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Ok((res, StatusStage {}))
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}
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}
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}
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}
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pub(crate) async fn accept_in(&mut self, buf: &[u8], stage: DataInStage) {
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pub(crate) async fn accept_in(&mut self, buf: &[u8], stage: DataInStage) {
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#[cfg(feature = "defmt")]
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#[cfg(feature = "defmt")]
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debug!("control in accept {:x}", buf);
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trace!(" control in accept {:02x}", buf);
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#[cfg(not(feature = "defmt"))]
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#[cfg(not(feature = "defmt"))]
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debug!("control in accept {:x?}", buf);
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trace!(" control in accept {:02x?}", buf);
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let req_len = stage.length;
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let req_len = stage.length;
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let len = buf.len().min(req_len);
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let len = buf.len().min(req_len);
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@ -305,10 +313,12 @@ impl<C: driver::ControlPipe> ControlPipe<C> {
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}
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}
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pub(crate) fn accept(&mut self, _: StatusStage) {
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pub(crate) fn accept(&mut self, _: StatusStage) {
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trace!(" control accept");
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self.control.accept();
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self.control.accept();
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}
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}
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pub(crate) fn reject(&mut self) {
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pub(crate) fn reject(&mut self) {
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trace!(" control reject");
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self.control.reject();
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self.control.reject();
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}
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}
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}
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}
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@ -128,14 +128,10 @@ impl<'d, D: Driver<'d>> UsbDevice<'d, D> {
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self.device_state = UsbDeviceState::Suspend;
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self.device_state = UsbDeviceState::Suspend;
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}
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}
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},
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},
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Either::Right(req) => {
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Either::Right(req) => match req {
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debug!("control request: {:x}", req);
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Setup::DataIn(req, stage) => self.handle_control_in(req, stage).await,
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Setup::DataOut(req, stage) => self.handle_control_out(req, stage).await,
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match req {
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},
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Setup::DataIn(req, stage) => self.handle_control_in(req, stage).await,
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Setup::DataOut(req, stage) => self.handle_control_out(req, stage).await,
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}
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}
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}
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}
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}
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}
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}
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}
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