rcc/bd: consolidate mod
This commit is contained in:
		| @@ -58,7 +58,7 @@ sdio-host = "0.5.0" | |||||||
| embedded-sdmmc = { git = "https://github.com/embassy-rs/embedded-sdmmc-rs", rev = "a4f293d3a6f72158385f79c98634cb8a14d0d2fc", optional = true } | embedded-sdmmc = { git = "https://github.com/embassy-rs/embedded-sdmmc-rs", rev = "a4f293d3a6f72158385f79c98634cb8a14d0d2fc", optional = true } | ||||||
| critical-section = "1.1" | critical-section = "1.1" | ||||||
| atomic-polyfill = "1.0.1" | atomic-polyfill = "1.0.1" | ||||||
| stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-2b87e34c661e19ff6dc603fabfe7fe99ab7261f7" } | stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-9a61a1f090462df8bd1751f89951f04934fdceb3" } | ||||||
| vcell = "0.1.3" | vcell = "0.1.3" | ||||||
| bxcan = "0.7.0" | bxcan = "0.7.0" | ||||||
| nb = "1.0.0" | nb = "1.0.0" | ||||||
| @@ -77,7 +77,7 @@ critical-section = { version = "1.1", features = ["std"] } | |||||||
| [build-dependencies] | [build-dependencies] | ||||||
| proc-macro2 = "1.0.36" | proc-macro2 = "1.0.36" | ||||||
| quote = "1.0.15" | quote = "1.0.15" | ||||||
| stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-2b87e34c661e19ff6dc603fabfe7fe99ab7261f7", default-features = false, features = ["metadata"]} | stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-9a61a1f090462df8bd1751f89951f04934fdceb3", default-features = false, features = ["metadata"]} | ||||||
|  |  | ||||||
| [features] | [features] | ||||||
| default = ["rt"] | default = ["rt"] | ||||||
|   | |||||||
| @@ -12,86 +12,67 @@ pub enum RtcClockSource { | |||||||
|     HSE = 0b11, |     HSE = 0b11, | ||||||
| } | } | ||||||
|  |  | ||||||
|  | #[cfg(not(any(rtc_v2l0, rtc_v2l1)))] | ||||||
|  | type Bdcr = crate::pac::rcc::regs::Bdcr; | ||||||
|  |  | ||||||
|  | #[cfg(any(rtc_v2l0, rtc_v2l1))] | ||||||
|  | type Bdcr = crate::pac::rcc::regs::Csr; | ||||||
|  |  | ||||||
| #[allow(dead_code)] | #[allow(dead_code)] | ||||||
| pub struct BackupDomain {} | pub struct BackupDomain {} | ||||||
|  |  | ||||||
| impl BackupDomain { | impl BackupDomain { | ||||||
|     #[cfg(any( |     #[cfg(any( | ||||||
|         rtc_v2f0, rtc_v2f2, rtc_v2f3, rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb |         rtc_v2f0, rtc_v2f2, rtc_v2f3, rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb, rtc_v3, | ||||||
|  |         rtc_v3u5 | ||||||
|     ))] |     ))] | ||||||
|     #[allow(dead_code)] |     #[allow(dead_code)] | ||||||
|     fn unlock_registers() { |     fn modify<R>(f: impl FnOnce(&mut Bdcr) -> R) -> R { | ||||||
|         #[cfg(any(rtc_v2f2, rtc_v2f3, rtc_v2l1))] |         #[cfg(any(rtc_v2f2, rtc_v2f3, rtc_v2l1))] | ||||||
|         let cr = crate::pac::PWR.cr(); |         let cr = crate::pac::PWR.cr(); | ||||||
|         #[cfg(any(rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l4, rtc_v2wb))] |         #[cfg(any(rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l4, rtc_v2wb, rtc_v3, rtc_v3u5))] | ||||||
|         let cr = crate::pac::PWR.cr1(); |         let cr = crate::pac::PWR.cr1(); | ||||||
|  |  | ||||||
|         // TODO: Missing from PAC for l0 and f0? |         // TODO: Missing from PAC for l0 and f0? | ||||||
|         #[cfg(not(any(rtc_v2f0, rtc_v2l0)))] |         #[cfg(not(any(rtc_v2f0, rtc_v2l0, rtc_v3u5)))] | ||||||
|         { |         { | ||||||
|             if !cr.read().dbp() { |             cr.modify(|w| w.set_dbp(true)); | ||||||
|                 cr.modify(|w| w.set_dbp(true)); |             while !cr.read().dbp() {} | ||||||
|                 while !cr.read().dbp() {} |  | ||||||
|             } |  | ||||||
|         } |         } | ||||||
|     } |  | ||||||
|  |  | ||||||
|     #[cfg(any(rtc_v3, rtc_v3u5))] |         crate::pac::RCC.bdcr().modify(|w| f(w)) | ||||||
|     #[allow(dead_code)] |  | ||||||
|     fn unlock_registers() { |  | ||||||
|         // Unlock the backup domain |  | ||||||
|         #[cfg(not(any(rtc_v3u5, rcc_wl5, rcc_wle)))] |  | ||||||
|         { |  | ||||||
|             if !crate::pac::PWR.cr1().read().dbp() { |  | ||||||
|                 crate::pac::PWR.cr1().modify(|w| w.set_dbp(true)); |  | ||||||
|                 while !crate::pac::PWR.cr1().read().dbp() {} |  | ||||||
|             } |  | ||||||
|         } |  | ||||||
|         #[cfg(any(rcc_wl5, rcc_wle))] |  | ||||||
|         { |  | ||||||
|             use crate::pac::pwr::vals::Dbp; |  | ||||||
|  |  | ||||||
|             if crate::pac::PWR.cr1().read().dbp() != Dbp::ENABLED { |  | ||||||
|                 crate::pac::PWR.cr1().modify(|w| w.set_dbp(Dbp::ENABLED)); |  | ||||||
|                 while crate::pac::PWR.cr1().read().dbp() != Dbp::ENABLED {} |  | ||||||
|             } |  | ||||||
|         } |  | ||||||
|     } |     } | ||||||
|  |  | ||||||
|     #[cfg(any( |     #[cfg(any( | ||||||
|         rtc_v2f0, rtc_v2f2, rtc_v2f3, rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb |         rtc_v2f0, rtc_v2f2, rtc_v2f3, rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb, rtc_v3, | ||||||
|  |         rtc_v3u5 | ||||||
|  |     ))] | ||||||
|  |     #[allow(dead_code)] | ||||||
|  |     fn read() -> Bdcr { | ||||||
|  |         #[cfg(any(rtc_v2l0, rtc_v2l1))] | ||||||
|  |         let r = crate::pac::RCC.csr().read(); | ||||||
|  |  | ||||||
|  |         #[cfg(not(any(rtc_v2l0, rtc_v2l1)))] | ||||||
|  |         let r = crate::pac::RCC.bdcr().read(); | ||||||
|  |  | ||||||
|  |         r | ||||||
|  |     } | ||||||
|  |  | ||||||
|  |     #[cfg(any( | ||||||
|  |         rtc_v2f0, rtc_v2f2, rtc_v2f3, rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb, rtc_v3, | ||||||
|  |         rtc_v3u5 | ||||||
|     ))] |     ))] | ||||||
|     #[allow(dead_code)] |     #[allow(dead_code)] | ||||||
|     pub fn set_rtc_clock_source(clock_source: RtcClockSource) { |  | ||||||
|         #[cfg(not(rtc_v2wb))] |  | ||||||
|         use stm32_metapac::rcc::vals::Rtcsel; |  | ||||||
|  |  | ||||||
|         #[cfg(not(any(rtc_v2l0, rtc_v2l1)))] |  | ||||||
|         let cr = crate::pac::RCC.bdcr(); |  | ||||||
|         #[cfg(any(rtc_v2l0, rtc_v2l1))] |  | ||||||
|         let cr = crate::pac::RCC.csr(); |  | ||||||
|  |  | ||||||
|         Self::unlock_registers(); |  | ||||||
|  |  | ||||||
|         cr.modify(|w| { |  | ||||||
|             // Select RTC source |  | ||||||
|             #[cfg(not(rtc_v2wb))] |  | ||||||
|             w.set_rtcsel(Rtcsel::from_bits(clock_source as u8)); |  | ||||||
|             #[cfg(rtc_v2wb)] |  | ||||||
|             w.set_rtcsel(clock_source as u8); |  | ||||||
|         }); |  | ||||||
|     } |  | ||||||
|  |  | ||||||
|     #[cfg(any(rtc_v3, rtc_v3u5))] |  | ||||||
|     #[allow(dead_code)] |  | ||||||
|     pub fn set_rtc_clock_source(clock_source: RtcClockSource) { |     pub fn set_rtc_clock_source(clock_source: RtcClockSource) { | ||||||
|         let clock_source = clock_source as u8; |         let clock_source = clock_source as u8; | ||||||
|         #[cfg(not(any(rcc_wl5, rcc_wle)))] |         #[cfg(any( | ||||||
|  |             all(not(any(rtc_v3, rtc_v3u5)), not(rtc_v2wb)), | ||||||
|  |             all(any(rtc_v3, rtc_v3u5), not(any(rcc_wl5, rcc_wle))) | ||||||
|  |         ))] | ||||||
|         let clock_source = crate::pac::rcc::vals::Rtcsel::from_bits(clock_source); |         let clock_source = crate::pac::rcc::vals::Rtcsel::from_bits(clock_source); | ||||||
|  |  | ||||||
|         Self::unlock_registers(); |         #[cfg(not(rtc_v2wb))] | ||||||
|  |         Self::modify(|w| { | ||||||
|         crate::pac::RCC.bdcr().modify(|w| { |  | ||||||
|             // Select RTC source |             // Select RTC source | ||||||
|             w.set_rtcsel(clock_source); |             w.set_rtcsel(clock_source); | ||||||
|         }); |         }); | ||||||
| @@ -102,25 +83,16 @@ impl BackupDomain { | |||||||
|     ))] |     ))] | ||||||
|     #[allow(dead_code)] |     #[allow(dead_code)] | ||||||
|     pub fn enable_rtc() { |     pub fn enable_rtc() { | ||||||
|         #[cfg(not(any(rtc_v2l0, rtc_v2l1)))] |         let reg = Self::read(); | ||||||
|         let reg = crate::pac::RCC.bdcr().read(); |  | ||||||
|         #[cfg(any(rtc_v2l0, rtc_v2l1))] |  | ||||||
|         let reg = crate::pac::RCC.csr().read(); |  | ||||||
|  |  | ||||||
|         #[cfg(any(rtc_v2h7, rtc_v2l4, rtc_v2wb))] |         #[cfg(any(rtc_v2h7, rtc_v2l4, rtc_v2wb))] | ||||||
|         assert!(!reg.lsecsson(), "RTC is not compatible with LSE CSS, yet."); |         assert!(!reg.lsecsson(), "RTC is not compatible with LSE CSS, yet."); | ||||||
|  |  | ||||||
|         if !reg.rtcen() { |         if !reg.rtcen() { | ||||||
|             Self::unlock_registers(); |  | ||||||
|  |  | ||||||
|             #[cfg(not(any(rtc_v2l0, rtc_v2l1, rtc_v2f2)))] |             #[cfg(not(any(rtc_v2l0, rtc_v2l1, rtc_v2f2)))] | ||||||
|             crate::pac::RCC.bdcr().modify(|w| w.set_bdrst(true)); |             Self::modify(|w| w.set_bdrst(true)); | ||||||
|             #[cfg(not(any(rtc_v2l0, rtc_v2l1)))] |  | ||||||
|             let cr = crate::pac::RCC.bdcr(); |  | ||||||
|             #[cfg(any(rtc_v2l0, rtc_v2l1))] |  | ||||||
|             let cr = crate::pac::RCC.csr(); |  | ||||||
|  |  | ||||||
|             cr.modify(|w| { |             Self::modify(|w| { | ||||||
|                 // Reset |                 // Reset | ||||||
|                 #[cfg(not(any(rtc_v2l0, rtc_v2l1)))] |                 #[cfg(not(any(rtc_v2l0, rtc_v2l1)))] | ||||||
|                 w.set_bdrst(false); |                 w.set_bdrst(false); | ||||||
| @@ -146,18 +118,13 @@ impl BackupDomain { | |||||||
|     #[cfg(any(rtc_v3, rtc_v3u5))] |     #[cfg(any(rtc_v3, rtc_v3u5))] | ||||||
|     #[allow(dead_code)] |     #[allow(dead_code)] | ||||||
|     pub fn enable_rtc() { |     pub fn enable_rtc() { | ||||||
|         let bdcr = crate::pac::RCC.bdcr(); |         let reg = Self::read(); | ||||||
|  |  | ||||||
|         let reg = bdcr.read(); |  | ||||||
|         assert!(!reg.lsecsson(), "RTC is not compatible with LSE CSS, yet."); |         assert!(!reg.lsecsson(), "RTC is not compatible with LSE CSS, yet."); | ||||||
|  |  | ||||||
|         if !reg.rtcen() { |         if !reg.rtcen() { | ||||||
|             Self::unlock_registers(); |             Self::modify(|w| w.set_bdrst(true)); | ||||||
|  |  | ||||||
|             bdcr.modify(|w| w.set_bdrst(true)); |             Self::modify(|w| { | ||||||
|  |  | ||||||
|             bdcr.modify(|w| { |  | ||||||
|                 // Reset |  | ||||||
|                 w.set_bdrst(false); |                 w.set_bdrst(false); | ||||||
|  |  | ||||||
|                 w.set_rtcen(true); |                 w.set_rtcen(true); | ||||||
|   | |||||||
| @@ -1,5 +1,4 @@ | |||||||
| pub use super::bus::{AHBPrescaler, APBPrescaler, VoltageScale}; | pub use super::bus::{AHBPrescaler, APBPrescaler, VoltageScale}; | ||||||
| use crate::pac::pwr::vals::Dbp; |  | ||||||
| use crate::pac::{FLASH, PWR, RCC}; | use crate::pac::{FLASH, PWR, RCC}; | ||||||
| use crate::rcc::bd::{BackupDomain, RtcClockSource}; | use crate::rcc::bd::{BackupDomain, RtcClockSource}; | ||||||
| use crate::rcc::{set_freqs, Clocks}; | use crate::rcc::{set_freqs, Clocks}; | ||||||
| @@ -212,7 +211,7 @@ pub(crate) unsafe fn init(config: Config) { | |||||||
|     match config.rtc_mux { |     match config.rtc_mux { | ||||||
|         RtcClockSource::LSE => { |         RtcClockSource::LSE => { | ||||||
|             // 1. Unlock the backup domain |             // 1. Unlock the backup domain | ||||||
|             PWR.cr1().modify(|w| w.set_dbp(Dbp::ENABLED)); |             PWR.cr1().modify(|w| w.set_dbp(true)); | ||||||
|  |  | ||||||
|             // 2. Setup the LSE |             // 2. Setup the LSE | ||||||
|             RCC.bdcr().modify(|w| { |             RCC.bdcr().modify(|w| { | ||||||
|   | |||||||
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