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Merge #921

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921: rp: fix nvic prio bits (it's 2, not 3) r=Dirbaio a=Dirbaio

bors r+

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
This commit is contained in:
bors[bot] 2022-08-22 14:30:06 +00:00 committed by GitHub
commit 53fbd0efb3
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2 changed files with 2 additions and 2 deletions
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2
embassy-rp/Cargo.toml
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@ -30,7 +30,7 @@ unstable-traits = ["embedded-hal-1"]
embassy-util = { version = "0.1.0", path = "../embassy-util" }
embassy-executor = { version = "0.1.0", path = "../embassy-executor" }
embassy-time = { version = "0.1.0", path = "../embassy-time", features = [ "tick-1mhz" ] }
embassy-cortex-m = { version = "0.1.0", path = "../embassy-cortex-m", features = ["prio-bits-3"]}
embassy-cortex-m = { version = "0.1.0", path = "../embassy-cortex-m", features = ["prio-bits-2"]}
embassy-hal-common = {version = "0.1.0", path = "../embassy-hal-common" }
embassy-embedded-hal = {version = "0.1.0", path = "../embassy-embedded-hal" }
atomic-polyfill = "1.0.1"

2
embassy-rp/src/gpio.rs
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@ -189,7 +189,7 @@ impl<'d, T: Pin> InputFuture<'d, T> {
unsafe {
let irq = interrupt::IO_IRQ_BANK0::steal();
irq.disable();
irq.set_priority(interrupt::Priority::P6);
irq.set_priority(interrupt::Priority::P3);
// Each INTR register is divided into 8 groups, one group for each
// pin, and each group consists of LEVEL_LOW, LEVEL_HIGH, EDGE_LOW,