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stm32g0: Fix ADC for channels above 14

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This commit is contained in:
Jaxter Kim 2022-11-14 14:56:30 +01:00
parent 2528f45138
commit 551b54ddcb
1 changed files with 2 additions and 2 deletions
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4
embassy-stm32/src/adc/v3.rs
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@ -71,7 +71,7 @@ impl<'d, T: Instance> Adc<'d, T> {
#[cfg(adc_g0)] #[cfg(adc_g0)]
T::regs().cfgr1().modify(|reg| { T::regs().cfgr1().modify(|reg| {
reg.set_chselrmod(true); reg.set_chselrmod(false);
}); });
} }
@ -200,7 +200,7 @@ impl<'d, T: Instance> Adc<'d, T> {
#[cfg(not(stm32g0))] #[cfg(not(stm32g0))]
T::regs().sqr1().write(|reg| reg.set_sq(0, pin.channel())); T::regs().sqr1().write(|reg| reg.set_sq(0, pin.channel()));
#[cfg(stm32g0)] #[cfg(stm32g0)]
T::regs().chselr().write(|reg| reg.set_chsel(pin.channel() as u32)); T::regs().chselr().write(|reg| reg.set_chsel(1 << pin.channel()));
// Some models are affected by an erratum: // Some models are affected by an erratum:
// If we perform conversions slower than 1 kHz, the first read ADC value can be // If we perform conversions slower than 1 kHz, the first read ADC value can be