stm32: update stm32-metapac.
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@ -73,14 +73,10 @@ impl<'a> TDesRing<'a> {
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// Initialize the pointers in the DMA engine. (There will be a memory barrier later
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// before the DMA engine is enabled.)
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// NOTE (unsafe) Used for atomic writes
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unsafe {
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let dma = ETH.ethernet_dma();
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dma.dmactx_dlar().write(|w| w.0 = descriptors.as_mut_ptr() as u32);
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dma.dmactx_rlr().write(|w| w.set_tdrl((descriptors.len() as u16) - 1));
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dma.dmactx_dtpr().write(|w| w.0 = 0);
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}
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let dma = ETH.ethernet_dma();
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dma.dmactx_dlar().write(|w| w.0 = descriptors.as_mut_ptr() as u32);
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dma.dmactx_rlr().write(|w| w.set_tdrl((descriptors.len() as u16) - 1));
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dma.dmactx_dtpr().write(|w| w.0 = 0);
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Self {
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descriptors,
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@ -129,8 +125,7 @@ impl<'a> TDesRing<'a> {
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}
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// signal DMA it can try again.
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// NOTE(unsafe) Atomic write
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unsafe { ETH.ethernet_dma().dmactx_dtpr().write(|w| w.0 = 0) }
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ETH.ethernet_dma().dmactx_dtpr().write(|w| w.0 = 0)
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}
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}
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@ -199,13 +194,10 @@ impl<'a> RDesRing<'a> {
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desc.set_ready(buffers[i].0.as_mut_ptr());
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}
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unsafe {
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let dma = ETH.ethernet_dma();
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dma.dmacrx_dlar().write(|w| w.0 = descriptors.as_mut_ptr() as u32);
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dma.dmacrx_rlr().write(|w| w.set_rdrl((descriptors.len() as u16) - 1));
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dma.dmacrx_dtpr().write(|w| w.0 = 0);
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}
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let dma = ETH.ethernet_dma();
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dma.dmacrx_dlar().write(|w| w.0 = descriptors.as_mut_ptr() as u32);
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dma.dmacrx_rlr().write(|w| w.set_rdrl((descriptors.len() as u16) - 1));
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dma.dmacrx_dtpr().write(|w| w.0 = 0);
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Self {
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descriptors,
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@ -254,8 +246,7 @@ impl<'a> RDesRing<'a> {
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fence(Ordering::Release);
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// signal DMA it can try again.
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// NOTE(unsafe) Atomic write
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unsafe { ETH.ethernet_dma().dmacrx_dtpr().write(|w| w.0 = 0) }
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ETH.ethernet_dma().dmacrx_dtpr().write(|w| w.0 = 0);
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// Increment index.
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self.index += 1;
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