stm32: update stm32-metapac.
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@ -46,7 +46,7 @@ impl<'d, T: Pin> Flex<'d, T> {
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/// Put the pin into input mode.
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#[inline]
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pub fn set_as_input(&mut self, pull: Pull) {
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critical_section::with(|_| unsafe {
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critical_section::with(|_| {
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let r = self.pin.block();
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let n = self.pin.pin() as usize;
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#[cfg(gpio_v1)]
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@ -84,7 +84,7 @@ impl<'d, T: Pin> Flex<'d, T> {
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/// at a specific level, call `set_high`/`set_low` on the pin first.
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#[inline]
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pub fn set_as_output(&mut self, speed: Speed) {
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critical_section::with(|_| unsafe {
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critical_section::with(|_| {
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let r = self.pin.block();
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let n = self.pin.pin() as usize;
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#[cfg(gpio_v1)]
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@ -116,7 +116,7 @@ impl<'d, T: Pin> Flex<'d, T> {
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/// at a specific level, call `set_high`/`set_low` on the pin first.
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#[inline]
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pub fn set_as_input_output(&mut self, speed: Speed, pull: Pull) {
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critical_section::with(|_| unsafe {
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critical_section::with(|_| {
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let r = self.pin.block();
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let n = self.pin.pin() as usize;
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#[cfg(gpio_v1)]
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@ -147,7 +147,7 @@ impl<'d, T: Pin> Flex<'d, T> {
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#[inline]
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pub fn is_low(&self) -> bool {
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let state = unsafe { self.pin.block().idr().read().idr(self.pin.pin() as _) };
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let state = self.pin.block().idr().read().idr(self.pin.pin() as _);
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state == vals::Idr::LOW
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}
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@ -164,7 +164,7 @@ impl<'d, T: Pin> Flex<'d, T> {
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/// Is the output pin set as low?
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#[inline]
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pub fn is_set_low(&self) -> bool {
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let state = unsafe { self.pin.block().odr().read().odr(self.pin.pin() as _) };
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let state = self.pin.block().odr().read().odr(self.pin.pin() as _);
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state == vals::Odr::LOW
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}
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@ -207,7 +207,7 @@ impl<'d, T: Pin> Flex<'d, T> {
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impl<'d, T: Pin> Drop for Flex<'d, T> {
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#[inline]
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fn drop(&mut self) {
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critical_section::with(|_| unsafe {
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critical_section::with(|_| {
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let r = self.pin.block();
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let n = self.pin.pin() as usize;
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#[cfg(gpio_v1)]
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@ -534,29 +534,25 @@ pub(crate) mod sealed {
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/// Set the output as high.
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#[inline]
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fn set_high(&self) {
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unsafe {
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let n = self._pin() as _;
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self.block().bsrr().write(|w| w.set_bs(n, true));
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}
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let n = self._pin() as _;
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self.block().bsrr().write(|w| w.set_bs(n, true));
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}
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/// Set the output as low.
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#[inline]
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fn set_low(&self) {
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unsafe {
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let n = self._pin() as _;
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self.block().bsrr().write(|w| w.set_br(n, true));
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}
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let n = self._pin() as _;
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self.block().bsrr().write(|w| w.set_br(n, true));
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}
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#[inline]
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unsafe fn set_as_af(&self, af_num: u8, af_type: AFType) {
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fn set_as_af(&self, af_num: u8, af_type: AFType) {
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self.set_as_af_pull(af_num, af_type, Pull::None);
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}
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#[cfg(gpio_v1)]
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#[inline]
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unsafe fn set_as_af_pull(&self, _af_num: u8, af_type: AFType, pull: Pull) {
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fn set_as_af_pull(&self, _af_num: u8, af_type: AFType, pull: Pull) {
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// F1 uses the AFIO register for remapping.
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// For now, this is not implemented, so af_num is ignored
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// _af_num should be zero here, since it is not set by stm32-data
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@ -599,7 +595,7 @@ pub(crate) mod sealed {
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#[cfg(gpio_v2)]
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#[inline]
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unsafe fn set_as_af_pull(&self, af_num: u8, af_type: AFType, pull: Pull) {
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fn set_as_af_pull(&self, af_num: u8, af_type: AFType, pull: Pull) {
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let pin = self._pin() as usize;
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let block = self.block();
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block.afr(pin / 8).modify(|w| w.set_afr(pin % 8, af_num));
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@ -614,7 +610,7 @@ pub(crate) mod sealed {
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}
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#[inline]
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unsafe fn set_as_analog(&self) {
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fn set_as_analog(&self) {
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let pin = self._pin() as usize;
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let block = self.block();
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#[cfg(gpio_v1)]
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@ -635,12 +631,12 @@ pub(crate) mod sealed {
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/// This is currently the same as set_as_analog but is semantically different really.
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/// Drivers should set_as_disconnected pins when dropped.
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#[inline]
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unsafe fn set_as_disconnected(&self) {
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fn set_as_disconnected(&self) {
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self.set_as_analog();
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}
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#[inline]
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unsafe fn set_speed(&self, speed: Speed) {
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fn set_speed(&self, speed: Speed) {
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let pin = self._pin() as usize;
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#[cfg(gpio_v1)]
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